System Specification and Design Languages : Selected Contributions from FDL 2010
This book brings together a selection of the best papers from the thirteenth edition of the Forum on specification and Design Languages Conference (FDL), which was held in Southampton, UK in September 2010. FDL is a well established international forum devoted to dissemination of research results,...
Guardat en:
| Altres autors: | , |
|---|---|
| Format: | Livre numérique |
| Idioma: | Anglais |
| Publicat: |
New York, NY :
Springer New York
[20..].
Cham : Springer Nature |
| Edició: | 1. |
| Col·lecció: | Lecture Notes in Electrical Engineering
106 |
| Accés en línia: | Accès sur la plateforme de l'éditeur Accès sur la plateforme Istex Accès Université d'Orléans Accès INSA CVL |
| Nota: |
Archives Springer e-books (Licence nationale) Archives Springer e-books (Licence nationale) |
| Autres localisations: | Voir dans le Sudoc |
| Edition sous un autre format: | • System Specification and Design Languages, Selected Contributions from FDL 2010, Tom J. Kaźmierski, Adam Morawiec, New York, NY, Springer Science+Business Media, LLC, 2012, 1 vol. (254 p.), Lecture Notes in Electrical Engineering, 978-1-4614-1426-1 |
Taula de continguts:
- Formal Hardware/Software Co-verification of Application Specific Instruction Set Processors Evaluating Debugging Algorithms from a Qualitative Perspective Mapping of Concurrent Object-oriented Models to Extend Real-time Task Networks SystemC-A Modelling of Mixed-technology Systems with Distributed Behaviour A Framework for Interactive Refinement of Mixed HW/SW/Analog Systems Bottom-up Verification for CMOS Photonic Linear Heterogeneous System Towards Abstract Analysis Techniques for Range Based System Simulations Modeling Time-triggered Architecture Based Real-time Systems Using SystemC Towards the Development of a Set of Transaction Level Models - A Feature-oriented Approach Rapid Prototyping of Complex HW/SW Systems Using a Timing and Power Aware ESL Framework Towards Accurate Source-level Annotation of Low-level Properties Obtained from Optimized Binary Code Architecture Specifications in C aSH SyReC: A Programming Language for Synthesis of Reversible Circuits Logical Time @ Work: Capturing Data Dependencies and Platform Constraints Formal Support for Untimed MARTE-SystemC Interoperability