Variation Tolerant On-Chip Interconnects
This book presents design techniques, analysis and implementation of high performance and power efficient, variation tolerant on-chip interconnects. Given the design paradigm shift to multi-core, interconnect-centric designs and the increase in sources of variability and their impact in sub-100nm t...
Enregistré dans:
| Hovedforfatter: | |
|---|---|
| Format: | Livre numérique |
| Sprog: | Anglais |
| Udgivet: |
New York, NY :
Springer New York
2012.
Cham : Springer Nature |
| Serier: | Analog Circuits and Signal Processing
|
| Online adgang: | Accès sur la plateforme de l'éditeur Accès sur la plateforme Istex Accès Université d'Orléans Accès INSA CVL |
| Kommentar: |
Archives Springer e-books (Licence nationale) Archives Springer e-books (Licence nationale) |
| Autres localisations: | Voir dans le Sudoc |
| Edition sous un autre format: | • Variation Tolerant On-Chip Interconnects, Texte imprimé, 9781461401308 • Variation Tolerant On-Chip Interconnects, Texte imprimé, 9781461401322 • Variation Tolerant On-Chip Interconnects, Texte imprimé, 9781489990860 |
Indholdsfortegnelse:
- Introduction
- On-Chip Communication
- Interconnect Design Techniques
- Design of Delay-Insensitive Current Sensing Interconnects
- Enhancing Completion Detection Performance
- Energy Efficient Semi-Serial Interconnect
- Comparison of the Designed Interconnects
- Circuit Techniques for PVT Variation Tolerance.