Higher-level hardware synthesis
In the mid 1960s, when a single chip contained an average of 50 transistors, Gordon Moore observed that integrated circuits were doubling in complexity every year. In an in?uential article published by Electronics Magazine in 1965, Moore predicted that this trend would continue for the next 10 years...
محفوظ في:
| المؤلف الرئيسي: | |
|---|---|
| التنسيق: | Livre numérique |
| اللغة: | Anglais |
| منشور في: |
Berlin [etc.] :
Springer
[20..].
Cham : Springer Nature |
| سلاسل: | Lecture notes in computer science
2963 |
| الموضوعات: | |
| الوصول للمادة أونلاين: | Accès sur la plateforme de l'éditeur Accès sur la plateforme Istex Accès Université d'Orléans Accès INSA CVL |
| ملاحظة: |
Archives Springer e-books (Licence nationale) Archives Springer e-books (Licence nationale) |
| Autres localisations: | Voir dans le Sudoc |
| Edition sous un autre format: | • Higher-level hardware synthesis, Richard Sharp, Berlin, Springer, 2004, 1 vol. (XVI-195 p.), Lecture notes in computer science, 3-540-21306-6 • Higher-Level Hardware Synthesis, Texte imprimé, 9783662197103 |
جدول المحتويات:
- 1. Introduction
- 1. Introduction
- 2. Related Work
- 3. The SAFL Language
- 4. Soft Scheduling
- 5. High-Level Synthesis of SAFL
- 6. Analysis and Optimisation of Intermediate Code
- 7. Dealing with I/O
- 8. Combining Behaviour and Structure
- 9. Transformation of SAFL Specifications
- 10. Case Study
- 11. Conclusions and Further Work.