Principles of VLSI RTL Design : A Practical Guide
In the process of integrated circuit design, front-end activities start with a register transfer level (RTL) description, of the functionality desired from the IC. During subsequent steps in the design flow, issues may arise related to testability, data synchronization across clock domains, synthesi...
Enregistré dans:
| Auteurs principaux: | , |
|---|---|
| Format: | Livre numérique |
| Sprog: | Anglais |
| Udgivet: |
New York, NY :
Springer New York
2011.
Cham : Springer Nature |
| Online adgang: | Accès sur la plateforme de l'éditeur Accès sur la plateforme Istex Accès Université d'Orléans Accès INSA CVL |
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Archives Springer e-books (Licence nationale) Archives Springer e-books (Licence nationale) |
| Autres localisations: | Voir dans le Sudoc |
| Edition sous un autre format: | • Principles of VLSI RTL Design, Texte imprimé, 9781441992956 • Principles of VLSI RTL Design, Texte imprimé, 9781441992970 • Principles of VLSI RTL Design, Texte imprimé, 9781489995452 |
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| 100 | 1 | |a Churiwala, Sanjay. | |
| 245 | 1 | 0 | |a Principles of VLSI RTL Design : |b A Practical Guide |c by Sanjay Churiwala, Sapan Garg. |
| 260 | |a New York, NY : |b Springer New York. | ||
| 260 | |a Cham : |b Springer Nature, |c 2011. | ||
| 500 | |a Archives Springer e-books (Licence nationale) | ||
| 500 | |a Archives Springer e-books (Licence nationale) | ||
| 506 | |a Accès en ligne pour les établissements français bénéficiaires des licences nationales | ||
| 506 | |a Accès soumis à abonnement pour tout autre établissement | ||
| 506 | |a Conditions particulières de réutilisation pour les bénéficiaires des licences nationales. chttps://www.licencesnationales.fr/springer-nature-ebooks-contrat-licence-ln-2017 | ||
| 520 | |a In the process of integrated circuit design, front-end activities start with a register transfer level (RTL) description, of the functionality desired from the IC. During subsequent steps in the design flow, issues may arise related to testability, data synchronization across clock domains, synthesizability, power consumption, routability, etc. which are a function of the way the RTL was originally written. As a result, RTL designers need to take care of many aspects which can have impact on later steps in the design process. Since RTL design is less about being a bright engineer, and more about knowing the downstream implications of your work, this book explains those various aspects, their significance, what caution needs to be taken during RTL design and why. Readers will benefit from a highly practical approach to the fundamentals of uncertainties around functionality, clock domain crossing and clock synchronization, design for test and testability, power consumption, static timing analysis, timing exception handling, and routing congestion. Hopefully, this book will find its place in the hearts and minds of anyone who generates RTL code. This includes RTL designers as well as those writing tools that generate RTL. Relatively new RTL designers will find this book to be a single-source of interesting, rich and useful knowledge. Experienced RTL designers will be able to appreciate and cement some already known concepts, given the focus on practical situations encountered in real designs. * Provides a highly accessible, single-source reference to all key topics essential to an RTL designer; * Describes in detail specific actions/cautions that designer needs to consider in design to avoid problems in downstream implementation; * Covers content based on practical experience with numerous real designs from large semiconductor design companies. . | ||
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| 776 | 0 | |t Principles of VLSI RTL Design |b Texte imprimé |z 9781441992970 | |
| 776 | 0 | |t Principles of VLSI RTL Design |b Texte imprimé |z 9781489995452 | |
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