High-Level Verification : Methods and Tools for Verification of System-Level Designs
This book looks at the problem of design verification with a view towards speeding up the process of verification by developing methods that apply to levels of abstraction above RTL or synchronous logic descriptions. Typically such descriptions capture design functionality at the system level, hence...
Enregistré dans:
| Auteurs principaux: | , , |
|---|---|
| Format: | Livre numérique |
| Langue: | Anglais |
| Publié: |
New York, NY :
Springer New York
2011.
Cham : Springer Nature |
| Accès en ligne: | Accès sur la plateforme de l'éditeur Accès sur la plateforme Istex Accès Université d'Orléans Accès INSA CVL |
| Note: |
Archives Springer e-books (Licence nationale) Archives Springer e-books (Licence nationale) |
| Autres localisations: | Voir dans le Sudoc |
| Edition sous un autre format: | • High-Level Verification, Texte imprimé, 9781441993588 • High-Level Verification, Texte imprimé, 9781441993601 • High-Level Verification, Texte imprimé, 9781493901012 |
Table des matières:
- Introduction
- Related Work
- Background
- Execution-based Model Checking for High-Level Designs
- Efficient Symbolic Analysis for Concurrent Programs
- Translation Validation of High-Level Synthesis
- Parameterized Program Equivalence Checking
- Conclusions and Future Work.