Low power networks-on-chip
Low Power Networks-on-Chip Edited by: (editors) Cristina Silvano Marcello Lajolo Gianluca Palermo In recent years, both Networks-on-Chip, as an architectural solution for high-speed interconnect, and power consumption, as a key design constraint, have continued to gain interest in the design and res...
Uloženo v:
| Další autoři: | , , |
|---|---|
| Médium: | Livre numérique |
| Jazyk: | Anglais |
| Vydáno: |
New York, NY :
Springer US
2011.
Cham : Springer Nature |
| On-line přístup: | Accès sur la plateforme de l'éditeur Accès sur la plateforme Istex Accès Université d'Orléans Accès INSA CVL |
| Poznámka: |
Archives Springer e-books (Licence nationale) Archives Springer e-books (Licence nationale) |
| Autres localisations: | Voir dans le Sudoc |
| Edition sous un autre format: | • Low Power Networks-on-Chip, Texte imprimé, 9781441969101 • Low Power Networks-on-Chip, Texte imprimé, 9781441969125 • Low Power Networks-on-Chip, Texte imprimé, 9781489994370 |
Obsah:
- Network-on-Chip Power Estimation
- Timing
- synchronous/asynchronous communication
- Network-on-Chip link design
- Topology exploration
- Network-on-Chip support for CMP/MPSoCs
- Network design for 3D stacked logic and memory
- Beyond the wired Network-on-Chip.