Low power networks-on-chip
Low Power Networks-on-Chip Edited by: (editors) Cristina Silvano Marcello Lajolo Gianluca Palermo In recent years, both Networks-on-Chip, as an architectural solution for high-speed interconnect, and power consumption, as a key design constraint, have continued to gain interest in the design and res...
Zapisane w:
| Kolejni autorzy: | , , |
|---|---|
| Format: | Livre numérique |
| Język: | Anglais |
| Wydane: |
New York, NY :
Springer US
2011.
Cham : Springer Nature |
| Dostęp online: | Accès sur la plateforme de l'éditeur Accès sur la plateforme Istex Accès Université d'Orléans Accès INSA CVL |
| Komentarz: |
Archives Springer e-books (Licence nationale) Archives Springer e-books (Licence nationale) |
| Autres localisations: | Voir dans le Sudoc |
| Edition sous un autre format: | • Low Power Networks-on-Chip, Texte imprimé, 9781441969101 • Low Power Networks-on-Chip, Texte imprimé, 9781441969125 • Low Power Networks-on-Chip, Texte imprimé, 9781489994370 |
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| 020 | |a 9781441969118 | ||
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| 245 | 0 | 0 | |a Low power networks-on-chip |c edited by Cristina Silvano, Marcello Lajolo, Gianluca Palermo. |
| 260 | |a New York, NY : |b Springer US. | ||
| 260 | |a Cham : |b Springer Nature, |c 2011. | ||
| 500 | |a Archives Springer e-books (Licence nationale) | ||
| 500 | |a Archives Springer e-books (Licence nationale) | ||
| 505 | 0 | |a Network-on-Chip Power Estimation -- Timing -- synchronous/asynchronous communication -- Network-on-Chip link design -- Topology exploration -- Network-on-Chip support for CMP/MPSoCs -- Network design for 3D stacked logic and memory -- Beyond the wired Network-on-Chip. | |
| 506 | |a Accès en ligne pour les établissements français bénéficiaires des licences nationales | ||
| 506 | |a Accès soumis à abonnement pour tout autre établissement | ||
| 506 | |a Conditions particulières de réutilisation pour les bénéficiaires des licences nationales. chttps://www.licencesnationales.fr/springer-nature-ebooks-contrat-licence-ln-2017 | ||
| 520 | |a Low Power Networks-on-Chip Edited by: (editors) Cristina Silvano Marcello Lajolo Gianluca Palermo In recent years, both Networks-on-Chip, as an architectural solution for high-speed interconnect, and power consumption, as a key design constraint, have continued to gain interest in the design and research communities, since power and energy issues still represent one of the limiting factors in integrating multi- and many-cores on a single chip. This book covers power and energy aware design techniques from several perspectives and abstraction levels and offers a single-source reference to some of the most important design techniques proposed in the context of low-power design for networks-on-chip architectures. Describes the most important design techniques that were invented, proposed, and applied to reduce both dynamic power and static power dissipation in networks-on-chip based architectures; Applies state-of-the-art, low-power design techniques to the design of Networks-on-Chip, to demonstrate methodology for design of high-speed, low-power interconnect; Offers a single source reference to the latest research, otherwise available only in disparate journals and conference proceedings. | ||
| 700 | 1 | |a Silvano, Cristina. |4 pbd | |
| 700 | 1 | |a Lajolo, Marcello. |4 pbd | |
| 700 | 1 | |a Palermo, Gianluca. |4 pbd | |
| 776 | 0 | |t Low Power Networks-on-Chip |b Texte imprimé |z 9781441969101 | |
| 776 | 0 | |t Low Power Networks-on-Chip |b Texte imprimé |z 9781441969125 | |
| 776 | 0 | |t Low Power Networks-on-Chip |b Texte imprimé |z 9781489994370 | |
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