Umamageswaran, K., Pandey, S. L., & Wilsey, P. A. Formal Semantics and Proof Techniques for Optimizing VHDL Models. Springer International Publishing.
Style de citation Chicago (17e éd.)Umamageswaran, Kothanda, Sheetanshu L. Pandey, et Philip A. Wilsey. Formal Semantics and Proof Techniques for Optimizing VHDL Models. Cham: Springer International Publishing.
Style de citation MLA (8e éd.)Umamageswaran, Kothanda, et al. Formal Semantics and Proof Techniques for Optimizing VHDL Models. Springer International Publishing.
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