Switch-Level Timing Simulation of MOS VLSI Circuits :: SCD d'Orléans

Switch-Level Timing Simulation of MOS VLSI Circuits

Switch-Level Timing Simulation of MOS VLSI Circuits

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Dades bibliogràfiques
Autors principals:	Rao, Vasant B., Trick, Timothy N. (Autor), Hajj, Ibrahim N. (Autor), Overhauser, David V. (Autor)
Format:	Livre numérique
Idioma:	Anglais
Publicat:	Cham : Springer International Publishing [20..]. Cham : Springer Nature
Accés en línia:	Accès sur la plateforme de l'éditeur Accès sur la plateforme Istex Accès Université d'Orléans Accès INSA CVL
Nota:	Autre(s) auteurs(s) : Ibrahim N. Hajj Archives Springer e-books (Licence nationale) Archives Springer e-books (Licence nationale)
Autres localisations:	Voir dans le Sudoc
Edition sous un autre format:	• Switch-Level Timing Simulation of MOS VLSI Circuits, 978-1-4612-8963-0

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