Error Control for Network-on-Chip Links
As technology scales into nanoscale regime, it is impossible to guarantee the perfect hardware design. Moreover, if the requirement of 100% correctness in hardware can be relaxed, the cost of manufacturing, verification, and testing will be significantly reduced. Many approaches have been proposed t...
Enregistré dans:
| Auteurs principaux: | , |
|---|---|
| Format: | Livre numérique |
| Sprog: | Anglais |
| Udgivet: |
New York, NY :
Springer New York
2012.
Cham : Springer Nature |
| Online adgang: | Accès sur la plateforme de l'éditeur Accès sur la plateforme Istex Accès Université d'Orléans Accès INSA CVL |
| Kommentar: |
Archives Springer e-books (Licence nationale) Archives Springer e-books (Licence nationale) |
| Autres localisations: | Voir dans le Sudoc |
| Edition sous un autre format: | • Error Control for Network-on-Chip Links, Texte imprimé, 9781441993120 • Error Control for Network-on-Chip Links, Texte imprimé, 9781441993144 • Error Control for Network-on-Chip Links, Texte imprimé, 9781489986337 |
Indholdsfortegnelse:
- Introduction
- Solutions to Improve the Reliability of On-Chip Interconnects
- Networks-on-Chip (NoC)
- Error Control Coding for On-Chip Interconnects
- Energy Efficient Error Control Implementation
- Combining Error Control Codes with Crosstalk Reduction.