Guide to FPGA implementation of arithmetic functions
This book is designed both for FPGA users interested in developing new, specific components - generally for reducing execution times and IP core designers interested in extending their catalog of specific components. The main focus is circuit synthesis and the discussion shows, for example, how a g...
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| Hlavní autoři: | , , |
|---|---|
| Médium: | Livre numérique |
| Jazyk: | Anglais |
| Vydáno: |
Dordrecht :
Springer Netherlands
2012.
Cham : Springer Nature |
| Edice: | Lecture Notes in Electrical Engineering
149 |
| On-line přístup: | Accès sur la plateforme de l'éditeur Accès sur la plateforme Istex Accès Université d'Orléans Accès INSA CVL |
| Poznámka: |
Archives Springer e-books (Licence nationale) Archives Springer e-books (Licence nationale) |
| Autres localisations: | Voir dans le Sudoc |
| Edition sous un autre format: | • Guide to FPGA Implementation of Arithmetic Functions, Jean-Pierre Deschamps, Gustavo D. Sutter, Enrique Cantó., Dordrecht, Springer Netherlands, 2014, 1 vol. (XV-469 p.), Lecture Notes in Electrical Engineering, 978-94-007-2986-5 |
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| 245 | 1 | 0 | |a Guide to FPGA implementation of arithmetic functions |c by Jean-Pierre Deschamps, Gustavo D. Sutter, Enrique Cantó. |
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| 505 | 1 | |a Basic Building Blocks Architecture of Digital Circuits Special Topics of Data Path Synthesis Control Unit Synthesis Electronic Aspects of Digital Design Electronic Aspects of Digital Design EDA Tools Adders Multipliers Dividers Other Operations Floating Point Arithmetic Finite-field Arithmetic Systems on Chip Embedded Systems Development: Case Studies Partial Reconfiguration on Xilinx FPGAs | |
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| 506 | |a Accès soumis à abonnement pour tout autre établissement | ||
| 506 | |a Conditions particulières de réutilisation pour les bénéficiaires des licences nationales. https://www.licencesnationales.fr/springer-nature-ebooks-contrat-licence-ln-2017 | ||
| 520 | |a This book is designed both for FPGA users interested in developing new, specific components - generally for reducing execution times and IP core designers interested in extending their catalog of specific components. The main focus is circuit synthesis and the discussion shows, for example, how a given algorithm executing some complex function can be translated to a synthesizable circuit description, as well as which are the best choices the designer can make to reduce the circuit cost, latency, or power consumption. This is not a book on algorithms. It is a book that shows how to translate efficiently an algorithm to a circuit, using techniques such as parallelism, pipeline, loop unrolling, and others. Numerous examples of FPGA implementation are described throughout this book and the circuits are modeled in VHDL. Complete and synthesizable source files are available for download | ||
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