Integrated circuit design : power and timing modeling, optimization, and simulation : 10th International Workshop, PATMOS 2000, Göttingen, Germany, September 13-15, 2000 : proceedings
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| 言語: | Anglais |
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| Edition sous un autre format: | • Integrated circuit design, power and timing modeling, optimization, and simulation, 10th International Workshop, PATMOS 2000, Göttingen, Germany, September 13-15, 2000, proceedings, Dimitrios Soudris, Peter Pirsch, Erich Barke (eds.), 2000, New York, Springer, 1 vol. (XII-338 p.), Lecture notes in computer science, 3-540-41068-6 • Integrated Circuit Design: Power and Timing Modeling, Optimization and Simulation, Texte imprimé, 9783662187272 |
目次:
- Opening
- Constraints, Hurdles and Opportunities for a Successful European Take-Up Action
- RTL Power Modeling
- Architectural Design Space Exploration Achieved through Innovative RTL Power Estimation Techniques
- Power Models for Semi-autonomous RTL Macros
- Power Macro-Modelling for Firm-Macro
- RTL Estimation of Steering Logic Power
- Power Estimation and Optimization
- Reducing Power Consumption through Dynamic Frequency Scaling for a Class of Digital Receivers
- Framework for High-Level Power Estimation of Signal Processing Architectures
- Adaptive Bus Encoding Technique for Switching Activity Reduced Data Transfer over Wide System Buses
- Accurate Power Estimation of Logic Structures Based on Timed Boolean Functions
- System-Level Design
- A Holistic Approach to System Level Energy Optimization
- Early Power Estimation for System-on-Chip Designs
- Design-Space Exploration of Low Power Coarse Grained Reconfigurable Datapath Array Architectures
- Transistor-Level Modeling
- Internal Power Dissipation Modeling and Minimization for Submicronic CMOS Design
- Impact of Voltage Scaling on Glitch Power Consumption
- Degradation Delay Model Extension to CMOS Gates
- Second Generation Delay Model for Submicron CMOS Process
- Asynchronous Circuit Design
- Semi-modular Latch Chains for Asynchronous Circuit Design
- Asynchronous First-in First-out Queues
- Comparative Study on Self-Checking Carry-Propagate Adders in Terms of Area, Power and Performance
- VLSI Implementation of a Low-Power High-Speed Self-Timed Adder
- Power Efficient Technologies
- Low Power Design Techniques for Contactless Chipcards
- Dynamic Memory Design for Low Data-Retention Power
- Double-Latch Clocking Scheme for Low-Power I.P. Cores
- Design of Multimedia Processing Applications
- Architecture, Design, and Verification of an 18 Million Transistor Digital Television and Media Processor Chip
- Cost-Efficient C-Level Design of an MPEG-4 Video Decoder
- Data-Reuse and Parallel Embedded Architectures for Low-Power, Real-Time Multimedia Applications
- AdiabaticDesign and ArithmeticModules
- Design of Reversible Logic Circuits by Means of Control Gates
- Modeling of Power Consumption of Adiabatic Gates versus Fan in and Comparison with Conventional Gates
- An Adiabatic Multiplier
- Logarithmic Number System for Low-Power Arithmetic
- Analog-Digital Circuits Modeling
- An Application of Self-Timed Circuits to the Reduction of Switching Noise in Analog-Digital Circuits
- PARCOURS Substrate Crosstalk Analysis for Complex Mixed-Signal-Circuits
- Influence of Clocking Strategies on the Design of Low Switching-Noise Digital and Mixed-Signal VLSI Circuits
- Computer Aided Generation of Analytic Models for Nonlinear Function Blocks.