Software and compilers for embedded systems : 7th international workshop, SCOPES 2003, Vienna, Austria, September 24-26, 2003 : proceedings
This volume contains the proceedings of the 7th International Workshop on Software and Compilers for Embedded Systems, SCOPES 2003, held in Vienna, Austria, September 24 26, 2003. Initially, the workshop was referred to as the International Workshop on Code Generation for Embedded Systems. The ?rst...
Kaydedildi:
| Müşterek Yazar: | |
|---|---|
| Diğer Yazarlar: | |
| Materyal Türü: | Livre numérique |
| Dil: | Anglais |
| Baskı/Yayın Bilgisi: |
Berlin [etc.] :
Springer
[20..].
Cham : Springer Nature |
| Seri Bilgileri: | Lecture notes in computer science
2826 |
| Konular: | |
| Online Erişim: | Accès sur la plateforme de l'éditeur Accès sur la plateforme Istex Accès Université d'Orléans Accès INSA CVL |
| Not: |
Archives Springer e-books (Licence nationale) Archives Springer e-books (Licence nationale) |
| Autres localisations: | Voir dans le Sudoc |
| Edition sous un autre format: | • Software and compilers for embedded systems, 7th international workshop, SCOPES 2003, Vienna, Austria, September 24-26, 2003, proceedings, Andreas Krall (ed.), Berlin, Springer, 2003, 1 vol. (XI-402 p.), Lecture notes in computer science, 3-540-20145-9 • Software and Compilers for Embedded Systems, Texte imprimé, 9783662165164 |
İçindekiler:
- Invited Talk
- The Transmeta Crusoe: VLIW Embedded in CISC
- Code Size Reduction
- Limited Address Range Architecture for Reducing Code Size in Embedded Processors
- Predicated Instructions for Code Compaction
- Code Generation for a Dual Instruction Set Processor Based on Selective Code Transformation
- Code Selection
- Code Instruction Selection Based on SSA-Graphs
- A Code Selection Method for SIMD Processors with PACK Instructions
- Reconstructing Control Flow from Predicated Assembly Code
- Loop Optimizations
- Control Flow Analysis for Recursion Removal
- An Unfolding-Based Loop Optimization Technique
- Tailoring Software Pipelining for Effective Exploitation of Zero Overhead Loop Buffer
- Automatic Retargeting
- Case Studies on Automatic Extraction of Target-Specific Architectural Parameters in Complex Code Generation
- Extraction of Efficient Instruction Schedulers from Cycle-True Processor Models
- System Design
- A Framework for the Design and Validation of Efficient Fail-Safe Fault-Tolerant Programs
- A Case Study on a Component-Based System and Its Configuration
- Composable Code Generation for Model-Based Development
- Code Generation for Packet Header Intrusion Analysis on the IXP1200 Network Processor
- Register Allocation
- Retargetable Graph-Coloring Register Allocation for Irregular Architectures
- Fine-Grain Register Allocation Based on a Global Spill Costs Analysis
- Offset Assignment
- Unified Instruction Reordering and Algebraic Transformations for Minimum Cost Offset Assignment
- Improving Offset Assignment through Simultaneous Variable Coalescing
- Analysis and Profiling
- Transformation of Meta-Information by Abstract Co-interpretation
- Performance Analysis for Identification of (Sub-)Task-Level Parallelism in Java
- Towards Superinstructions for Java Interpreters
- Memory and Cache Optimizations
- Partitioning for DSP Software Synthesis
- Efficient Variable Allocation to Dual Memory Banks of DSPs
- Cache Behavior Modeling of Codes with Data-Dependent Conditionals
- FICO: A Fast Instruction Cache Optimizer.