Power-aware computer systems : first International Workshop, PACS 2000, Cambridge, MA, USA, November 12, 2000 : revised papers
The phenomenal increases in computer system performance in recent years have been accompanied by a commensurate increase in power and energy dissipation. The latter has directly resulted in demand for expensive packaging and cooling technology, an increase in product cost, and a decrease in product...
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| Format: | Livre numérique |
| Idioma: | Anglais |
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Berlin [etc.] :
Springer
[20..].
Cham : Springer Nature |
| Col·lecció: | Lecture notes in computer science
2008 |
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| Accés en línia: | Accès sur la plateforme de l'éditeur Accès sur la plateforme Istex Accès Université d'Orléans Accès INSA CVL |
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Archives Springer e-books (Licence nationale) Archives Springer e-books (Licence nationale) |
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| Edition sous un autre format: | • Power-aware computer systems, first International Workshop, PACS 2000, Cambridge, MA, USA, November 12, 2000, revised papers, Babak Falsafi, T.N. Vijaykumar, (Eds.), 2001, New York, Springer, 1 vol. (X-151 p.), Lecture notes in computer science, 3-540-42329-X • Power-Aware Computer Systems, Texte imprimé, 9783662162897 |
Taula de continguts:
- Power-Aware Microarchitectural/Circuit Techniques
- System-Level Design Methods for Low-Energy Architectures Containing Variable Voltage Processors
- Ramp Up/Down Functional Unit to Reduce Step Power
- An Adaptive Issue Queue for Reduced Power at High Performance
- Application/Compiler Optimizations
- Dynamic Memory Oriented Transformations in the MPEG4 IM1-Player on a Low Power Platform
- Exploiting Content Variation and Perception in Power-Aware 3D Graphics Rendering
- Compiler-Directed Dynamic Frequency and Voltage Scheduling
- Exploiting IPC/Memory Slack
- Cache-Line Decay: A Mechanism to Reduce Cache Leakage Power
- Dynamically Reconfiguring Processor Resources to Reduce Power Consumption in High-Performance Processors
- Power/Performance Models and Tools
- TEM2P2EST: A Thermal Enabled Multi-model Power/Performance ESTimator
- Power-Performance Modeling and Tradeoff Analysis for a High End Microprocessor
- A Comparison of Two Architectural Power Models.