Formal methods in computer-aided design : third international conference, FMCAD 2000, Austin, Texas, USA, November 1-3, 2000 : proceedings
The biannual Formal Methods in Computer Aided Design conference (FMCAD 2000)is the third in a series of conferences under that title devoted to the use of discrete mathematical methods for the analysis of computer hardware and so- ware. The work reported in this book describes the use of modeling la...
Guardat en:
| Autor corporatiu: | |
|---|---|
| Altres autors: | , |
| Format: | Livre numérique |
| Idioma: | Anglais |
| Publicat: |
Berlin [etc.] :
Springer
[20..].
Cham : Springer Nature |
| Col·lecció: | Lecture notes in computer science
1954 |
| Matèries: | |
| Accés en línia: | Accès sur la plateforme de l'éditeur Accès sur la plateforme Istex Accès Université d'Orléans Accès INSA CVL |
| Nota: |
Archives Springer e-books (Licence nationale) Archives Springer e-books (Licence nationale) |
| Autres localisations: | Voir dans le Sudoc |
| Edition sous un autre format: | • Formal methods in computer-aided design, third international conference, FMCAD 2000, Austin, Texas, USA, November 1-3, 2000, proceedings, Warren A. Hunt, Jr., Steven D. Johnson, eds, 2000, New York, Springer, 1 vol (XI-537 p.), Lecture notes in computer science, 3-540-41219-0 • Formal Methods in Computer-Aided Design, Texte imprimé, 9783662211731 |
Taula de continguts:
- Applications of Hierarchical Verification in Model Checking
- Applications of Hierarchical Verification in Model Checking
- Invited Talk
- Trends in Computing
- Invited Paper
- A Case Study in Formal Verification of Register-Transfer Logic with ACL2: The Floating Point Adder of the AMD Athlon TM Processor
- Contributed Papers
- An Algorithm for Strongly Connected Component Analysis in n log n Symbolic Steps
- Automated Refinement Checking for Asynchronous Processes
- Border-Block Triangular Form and Conjunction Schedule in Image Computation
- B2M: A Semantic Based Tool for BLIF Hardware Descriptions
- Checking Safety Properties Using Induction and a SAT-Solver
- Combining Stream-Based and State-Based Verification Techniques
- A Comparative Study of Symbolic Algorithms for the Computation of Fair Cycles
- Correctness of Pipelined Machines
- Do You Trust Your Model Checker?
- Executable Protocol Specification in ESL
- Formal Verification of Floating Point Trigonometric Functions
- Hardware Modeling Using Function Encapsulation
- A Methodology for the Formal Analysis of Asynchronous Micropipelines
- A Methodology for Large-Scale Hardware Verification
- Model Checking Synchronous Timing Diagrams
- Model Reductions and a Case Study
- Modeling and Parameters Synthesis for an Air TrafficManagement System
- Monitor-Based Formal Specification of PCI
- SAT-Based Image Computation with Application in Reachability Analysis
- SAT-Based Verification without State Space Traversal
- Scalable Distributed On-the-Fly Symbolic Model Checking
- The Semantics of Verilog Using Transition System Combinators
- Sequential Equivalence Checking by Symbolic Simulation
- Speeding Up Image Computation by Using RTL Information
- Symbolic Checking of Signal-Transition Consistency for Verifying High-Level Designs
- Symbolic Simulation with Approximate Values
- A Theory of Consistency for Modular Synchronous Systems
- Verifying Transaction Ordering Properties in Unbounded Bus Networks through Combined Deductive/Algorithmic Methods
- Visualizing System Factorizations with Behavior Tables.