Concurrency and hardware design : advances in Petri nets
As CMOS semiconductor technology strides towards billions of transistors on a single die new problems arise on the way. They are concerned with the - minishing fabrication process features, which a?ect for example the gate-to-wire delay ratio. They manifest themselves in greater variations of size a...
Salvato in:
| Autore principale: | |
|---|---|
| Altri autori: | , |
| Natura: | Livre numérique |
| Lingua: | Anglais |
| Pubblicazione: |
Berlin [etc.] :
Springer
[20..].
Cham : Springer Nature |
| Serie: | Lecture notes in computer science
2549 |
| Soggetti: | |
| Accesso online: | Accès sur la plateforme de l'éditeur Accès sur la plateforme Istex Accès Université d'Orléans Accès INSA CVL |
| Nota: |
Archives Springer e-books (Licence nationale) Archives Springer e-books (Licence nationale) |
| Autres localisations: | Voir dans le Sudoc |
| Edition sous un autre format: | • Concurrency and hardware design, advances in Petri nets, Jordi Cortadella, Alex Yakovlev, Gezegorz Rozenberg (eds.), Berlin, Springer, 2002, 1 vol. (IX-343 p.), Lecture notes in computer science, 3-540-00199-9 • Concurrency and Hardware Design, Texte imprimé, 9783662176610 |
Sommario:
- Formal Models
- Composing Snippets
- A Programming Approach to the Design of Asynchronous Logic Blocks
- Asynchronous Circuits
- GALA (Globally Asynchronous Locally Arbitrary) Design
- Synthesis of Reactive Systems: Application to Asynchronous Circuit Design
- Decomposition in Asynchronous Circuit Design
- Embedded System Design
- Functional and Performance Modeling of Concurrency in VCC
- Modeling and Designing Heterogeneous Systems
- Timed Verification and Performance Analysis
- Timed Verification of Asynchronous Circuits
- Performance Analysis of Asynchronous Circuits Using Markov Chains.