Concurrency and hardware design : advances in Petri nets
As CMOS semiconductor technology strides towards billions of transistors on a single die new problems arise on the way. They are concerned with the - minishing fabrication process features, which a?ect for example the gate-to-wire delay ratio. They manifest themselves in greater variations of size a...
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| Schriftenreihe: | Lecture notes in computer science
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| Edition sous un autre format: | • Concurrency and hardware design, advances in Petri nets, Jordi Cortadella, Alex Yakovlev, Gezegorz Rozenberg (eds.), Berlin, Springer, 2002, 1 vol. (IX-343 p.), Lecture notes in computer science, 3-540-00199-9 • Concurrency and Hardware Design, Texte imprimé, 9783662176610 |
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| 100 | 1 | |a Cortadella, Jordi, |d 1962- | |
| 245 | 1 | 0 | |a Concurrency and hardware design : |b advances in Petri nets |c [edited by] Jordi Cortadella, Alex Yakovlev, Grzegorz Rozenberg. |
| 260 | |a Berlin [etc.] : |b Springer. | ||
| 260 | |a Cham : |b Springer Nature, |c [20..]. | ||
| 490 | 0 | |a Lecture notes in computer science |v 2549 |x 1611-3349 | |
| 500 | |a Archives Springer e-books (Licence nationale) | ||
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| 505 | 0 | |a Formal Models -- Composing Snippets -- A Programming Approach to the Design of Asynchronous Logic Blocks -- Asynchronous Circuits -- GALA (Globally Asynchronous Locally Arbitrary) Design -- Synthesis of Reactive Systems: Application to Asynchronous Circuit Design -- Decomposition in Asynchronous Circuit Design -- Embedded System Design -- Functional and Performance Modeling of Concurrency in VCC -- Modeling and Designing Heterogeneous Systems -- Timed Verification and Performance Analysis -- Timed Verification of Asynchronous Circuits -- Performance Analysis of Asynchronous Circuits Using Markov Chains. | |
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| 506 | |a Conditions particulières de réutilisation pour les bénéficiaires des licences nationales. https://www.licencesnationales.fr/springer-nature-ebooks-contrat-licence-ln-2017 | ||
| 520 | |a As CMOS semiconductor technology strides towards billions of transistors on a single die new problems arise on the way. They are concerned with the - minishing fabrication process features, which a?ect for example the gate-to-wire delay ratio. They manifest themselves in greater variations of size and operating parameters of devices, which put the overall reliability of systems at risk. And, most of all, they have tremendous impact on design productivity, where the costs of utilizing the growing silicon real estate rocket to billions of dollars that have to be spent on design, veri?cation, and testing. All such problems call for new - sign approaches and models for digital systems. Furthermore, new developments in non-CMOS technologies, such as single-electron transistors, rapid single-?- quantum devices, quantum dot cells, molecular devices, etc. , add extra demand for new research in system design methodologies. What kind of models and design methodologies will be required to build systems in all these new technologies? Answering this question, even for each particular type of new technology generation, is not easy, especially because sometimes it is not even clear what kind of elementary devices are feasible there. This problem is of an interdisciplinary nature. It requires an bridges between di?erent scienti?c communities. The bridges must be built very quickly, and be maximally ?exible to accommodate changes taking place in a logarithmic timescale. | ||
| 650 | |a Génie logiciel | ||
| 650 | |a Informatique | ||
| 650 | |a Petri, Réseaux de | ||
| 650 | |a Ordinateurs | ||
| 650 | |a Parallélisme (informatique) | ||
| 650 | |a Logique symbolique et mathématique | ||
| 650 | |a Ordinateurs | ||
| 700 | 1 | |a Yakovlev, Alexander B., |d 19..- |4 pbd | |
| 700 | 1 | |a Rozenberg, Grzegorz, |d 1942- |4 pbd | |
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| 776 | 0 | |t Concurrency and Hardware Design |b Texte imprimé |z 9783662176610 | |
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