Formal methods in computer aided design : second international conference, FMCAD '98, Palo Alto, CA, USA, November 4-6, 1998 : proceedings
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| Format: | Livre numérique |
| Sprog: | Anglais |
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Springer
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Cham : Springer Nature |
| Serier: | Lecture notes in computer science
1522 |
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| Online adgang: | Accès sur la plateforme de l'éditeur Accès sur la plateforme Istex Accès Université d'Orléans Accès INSA CVL |
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Archives Springer e-books (Licence nationale) Archives Springer e-books (Licence nationale) |
| Autres localisations: | Voir dans le Sudoc |
| Edition sous un autre format: | • Formal methods in computer aided design, second international conference, FMCAD '98, Palo Alto, CA, USA, November 4-6, 1998, proceedings, Ganesh Gopalakrishnan, Phillip Windley, eds, 1998, New York, Springer, 1 vol. (X-538 p.), Lecture notes in computer science, 3-540-65191-8 • Formal Methods in Computer-Aided Design, Texte imprimé, 9783662204689 |
Indholdsfortegnelse:
- Minimalist Proof Assistants: Interactions of Technology and Methodology in Formal System Level Verification
- Reducing Manual Abstraction in Formal Verification of Out- of- Order Execution
- Bit-Level Abstraction in the Verification of Pipelined Microprocessors by Correspondence Checking
- Solving Bit-Vector Equations
- The Formal Design of 1M-Gate ASICs
- Design of Experiments for Evaluation of BDD Packages Using Controlled Circuit Mutations
- A Tutorial on Stålmarck s Proof Procedure for Propositional Logic
- Almana: A BDD Minimization Tool Integrating Heuristic and RewritingMethods
- Bisimulation Minimization in an Automata-Theoretic Verification Framework
- Automatic Verification of Mixed-Level Logic Circuits
- A Timed Automaton-Based Method for Accurate Computation of Circuit Delay in the Presence of Cross-Talk
- Maximum Time Separation of Events in Cyclic Systems with Linear and Latest Timing Constraints
- Using MTBDDs for Composition and Model Checking of Real-Time Systems
- Formal Methods in CAD from an Industrial Perspective
- A Methodology for Automated Verification of Synthesized RTL Designs and Its Integration with a High-Level Synthesis Tool
- Combined Formal Post- and Presynthesis Verification in High Level Synthesis
- Formalization and Proof of a Solution to the PCI 2.1 Bus Transaction Ordering Problem
- A Performance Study of BDD-Based Model Checking
- Symbolic Model Checking Visualization
- Input Elimination and Abstraction in Model Checking
- Symbolic Simulation of the JEM1 Microprocessor
- Symbolic Simulation: An ACL2 Approach
- Verification of Data-Insensitive Circuits: An In-Order-Retirement Case Study
- Combining Symbolic Model Checking with Uninterpreted Functions for Out-of-Order Processor Verification
- Formally Verifying Data and Controlwith Weak Reachability Invariants
- Generalized Reversible Rules
- An Assume-Guarantee Rule for Checking Simulation
- Three Approaches to Hardware Verification: HOL, MDG, and VIS Compared
- An Instruction Set Process Calculus
- Techniques for Implicit State Enumeration of EFSMs
- Model Checking on Product Structures
- BDDNOW: A Parallel BDD Package
- Model Checking VHDL with CV
- Alexandria: A Tool for Hierarchical Verification
- PV: An Explicit Enumeration Model-Checker.