Formal methods in computer aided design : second international conference, FMCAD '98, Palo Alto, CA, USA, November 4-6, 1998 : proceedings
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| Outros autores: | , |
| Formato: | Livre numérique |
| Idioma: | Anglais |
| Publicado: |
Berlin [etc.] :
Springer
[20..].
Cham : Springer Nature |
| Series: | Lecture notes in computer science
1522 |
| Sujets: | |
| Acceso en liña: | Accès sur la plateforme de l'éditeur Accès sur la plateforme Istex Accès Université d'Orléans Accès INSA CVL |
| Nota: |
Archives Springer e-books (Licence nationale) Archives Springer e-books (Licence nationale) |
| Autres localisations: | Voir dans le Sudoc |
| Edition sous un autre format: | • Formal methods in computer aided design, second international conference, FMCAD '98, Palo Alto, CA, USA, November 4-6, 1998, proceedings, Ganesh Gopalakrishnan, Phillip Windley, eds, 1998, New York, Springer, 1 vol. (X-538 p.), Lecture notes in computer science, 3-540-65191-8 • Formal Methods in Computer-Aided Design, Texte imprimé, 9783662204689 |
| LEADER | 05065nam a22004577a 4500 | ||
|---|---|---|---|
| 001 | 948593 | ||
| 008 | 110927q2000 xxe ||| |||| 00| 0 eng d | ||
| 009 | PPN155174320 | ||
| 020 | |a 9783540495192 (PDF) | ||
| 041 | 0 | |a eng | |
| 082 | |a 004 | ||
| 082 | |a 621.392 | ||
| 111 | 2 | |a International conference on Formal Methods in Computer-Aided Design |n (02 |d :1998 |c :Palo Alto, Calif.). | |
| 245 | 1 | 0 | |a Formal methods in computer aided design : |b second international conference, FMCAD '98, Palo Alto, CA, USA, November 4-6, 1998 : proceedings |c [edited by] Ganesh Gopalakrishnan, Phillip Windley. |
| 260 | |a Berlin [etc.] : |b Springer. | ||
| 260 | |a Cham : |b Springer Nature, |c [20..]. | ||
| 490 | 0 | |a Lecture notes in computer science |v 1522 |x 1611-3349 | |
| 500 | |a Archives Springer e-books (Licence nationale) | ||
| 500 | |a Archives Springer e-books (Licence nationale) | ||
| 505 | 0 | |a Minimalist Proof Assistants: Interactions of Technology and Methodology in Formal System Level Verification -- Reducing Manual Abstraction in Formal Verification of Out- of- Order Execution -- Bit-Level Abstraction in the Verification of Pipelined Microprocessors by Correspondence Checking -- Solving Bit-Vector Equations -- The Formal Design of 1M-Gate ASICs -- Design of Experiments for Evaluation of BDD Packages Using Controlled Circuit Mutations -- A Tutorial on Stålmarck s Proof Procedure for Propositional Logic -- Almana: A BDD Minimization Tool Integrating Heuristic and RewritingMethods -- Bisimulation Minimization in an Automata-Theoretic Verification Framework -- Automatic Verification of Mixed-Level Logic Circuits -- A Timed Automaton-Based Method for Accurate Computation of Circuit Delay in the Presence of Cross-Talk -- Maximum Time Separation of Events in Cyclic Systems with Linear and Latest Timing Constraints -- Using MTBDDs for Composition and Model Checking of Real-Time Systems -- Formal Methods in CAD from an Industrial Perspective -- A Methodology for Automated Verification of Synthesized RTL Designs and Its Integration with a High-Level Synthesis Tool -- Combined Formal Post- and Presynthesis Verification in High Level Synthesis -- Formalization and Proof of a Solution to the PCI 2.1 Bus Transaction Ordering Problem -- A Performance Study of BDD-Based Model Checking -- Symbolic Model Checking Visualization -- Input Elimination and Abstraction in Model Checking -- Symbolic Simulation of the JEM1 Microprocessor -- Symbolic Simulation: An ACL2 Approach -- Verification of Data-Insensitive Circuits: An In-Order-Retirement Case Study -- Combining Symbolic Model Checking with Uninterpreted Functions for Out-of-Order Processor Verification -- Formally Verifying Data and Controlwith Weak Reachability Invariants -- Generalized Reversible Rules -- An Assume-Guarantee Rule for Checking Simulation -- Three Approaches to Hardware Verification: HOL, MDG, and VIS Compared -- An Instruction Set Process Calculus -- Techniques for Implicit State Enumeration of EFSMs -- Model Checking on Product Structures -- BDDNOW: A Parallel BDD Package -- Model Checking VHDL with CV -- Alexandria: A Tool for Hierarchical Verification -- PV: An Explicit Enumeration Model-Checker. | |
| 506 | |a Accès en ligne pour les établissements français bénéficiaires des licences nationales | ||
| 506 | |a Accès soumis à abonnement pour tout autre établissement | ||
| 506 | |a Conditions particulières de réutilisation pour les bénéficiaires des licences nationales. https://www.licencesnationales.fr/springer-nature-ebooks-contrat-licence-ln-2017 | ||
| 650 | |a Conception assistée par ordinateur | ||
| 650 | |a Informatique | ||
| 650 | |a Circuits intégrés | ||
| 650 | |a Génie logiciel | ||
| 650 | |a Logique symbolique et mathématique | ||
| 650 | |a Théorèmes |x Démonstration automatique | ||
| 650 | |a Ordinateurs | ||
| 650 | |a Circuits intégrés numériques |x Conception technique -- Informatique | ||
| 650 | |a Actes de congrès | ||
| 700 | 1 | |a Windley, Phillip J., |d 1958- |4 pbd | |
| 700 | 1 | |a Gopalakrishnan, Ganesh. |4 pbd | |
| 776 | 0 | |0 04544417X |t Formal methods in computer aided design |o second international conference, FMCAD '98, Palo Alto, CA, USA, November 4-6, 1998 |o proceedings |f Ganesh Gopalakrishnan, Phillip Windley, eds |d 1998 |c New York |n Springer |p 1 vol. (X-538 p.) |s Lecture notes in computer science |z 3-540-65191-8 | |
| 776 | 0 | |t Formal Methods in Computer-Aided Design |b Texte imprimé |z 9783662204689 | |
| 856 | 4 | |q PDF |u https://doi.org/10.1007/3-540-49519-3 |z Accès sur la plateforme de l'éditeur | |
| 856 | 4 | |u https://revue-sommaire.istex.fr/ark:/67375/8Q1-S1RSN603-C |z Accès sur la plateforme Istex | |
| 856 | 4 | |5 452349901:748059172 |u https://ezproxy.univ-orleans.fr/login?url=https://doi.org/10.1007/3-540-49519-3 |z Accès Université d'Orléans | |
| 856 | 4 | |5 180339901:751510688 |u https://ezproxy.insa-cvl.fr/login?qurl=https://doi.org/10.1007/3-540-49519-3 |z Accès INSA CVL | |
| 997 | |0 948593 |1 Livre numérique |a Ressource numérique |b INSA |b ENSA |c 0/Bibliothèque numérique/ |c 1/Bibliothèque numérique/Autre ressource numérique/ | ||