System-level test and validation of hardware/software systems
New manufacturing technologies have made possible the integration of entire systems on a single chip. This new design paradigm, termed system-on-chip (SOC), together with its associated manufacturing problems, represents a real challenge for designers. As well as giving rise to new design practices,...
Guardat en:
| Autor principal: | |
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| Altres autors: | , |
| Format: | Livre numérique |
| Idioma: | Anglais |
| Publicat: |
London :
Springer London
2005.
Cham : Springer Nature |
| Col·lecció: | Springer Series in Advanced Microelectronics
17 |
| Accés en línia: | Accès sur la plateforme de l'éditeur Accès sur la plateforme Istex Accès Université d'Orléans Accès INSA CVL |
| Nota: |
Archives Springer e-books (Licence nationale) Archives Springer e-books (Licence nationale) |
| Autres localisations: | Voir dans le Sudoc |
| Edition sous un autre format: | • System-level Test and Validation of Hardware/Software Systems, Texte imprimé, 9781849969536 • System-level Test and Validation of Hardware/Software Systems, Texte imprimé, 9781848008076 • System-level Test and Validation of Hardware/Software Systems, Texte imprimé, 9781852338992 |
Taula de continguts:
- Modeling Permanent Faults
- Test Generation: A Symbolic Approach
- Test Generation: A Heuristic Approach
- Test Generation: A Hierarchical Approach
- Test Program Generation from High-level Microprocessor Descriptions
- Tackling Concurrency and Timing Problems
- An Approach to System-level Design for Test
- System-level Dependability Analysis.