System-level test and validation of hardware/software systems
New manufacturing technologies have made possible the integration of entire systems on a single chip. This new design paradigm, termed system-on-chip (SOC), together with its associated manufacturing problems, represents a real challenge for designers. As well as giving rise to new design practices,...
Shranjeno v:
| Glavni avtor: | |
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| Drugi avtorji: | , |
| Format: | Livre numérique |
| Jezik: | Anglais |
| Izdano: |
London :
Springer London
2005.
Cham : Springer Nature |
| Serija: | Springer Series in Advanced Microelectronics
17 |
| Online dostop: | Accès sur la plateforme de l'éditeur Accès sur la plateforme Istex Accès Université d'Orléans Accès INSA CVL |
| Sporočilo: |
Archives Springer e-books (Licence nationale) Archives Springer e-books (Licence nationale) |
| Autres localisations: | Voir dans le Sudoc |
| Edition sous un autre format: | • System-level Test and Validation of Hardware/Software Systems, Texte imprimé, 9781849969536 • System-level Test and Validation of Hardware/Software Systems, Texte imprimé, 9781848008076 • System-level Test and Validation of Hardware/Software Systems, Texte imprimé, 9781852338992 |
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| 020 | |a 9781846281457 | ||
| 020 | |a 9781846281457 | ||
| 041 | 0 | |a eng | |
| 082 | |a 621.3815 | ||
| 100 | 1 | |a Sonza Reorda, Matteo. | |
| 245 | 1 | 0 | |a System-level test and validation of hardware/software systems |c edited by Matteo Sonza Reorda, Zebo Peng, Massimo Violante. |
| 260 | |a London : |b Springer London. | ||
| 260 | |a Cham : |b Springer Nature, |c 2005. | ||
| 490 | 0 | |a Springer Series in Advanced Microelectronics |v 17 |x 2197-6643 | |
| 500 | |a Archives Springer e-books (Licence nationale) | ||
| 500 | |a Archives Springer e-books (Licence nationale) | ||
| 505 | 0 | |a Modeling Permanent Faults -- Test Generation: A Symbolic Approach -- Test Generation: A Heuristic Approach -- Test Generation: A Hierarchical Approach -- Test Program Generation from High-level Microprocessor Descriptions -- Tackling Concurrency and Timing Problems -- An Approach to System-level Design for Test -- System-level Dependability Analysis. | |
| 506 | |a Accès en ligne pour les établissements français bénéficiaires des licences nationales | ||
| 506 | |a Accès soumis à abonnement pour tout autre établissement | ||
| 506 | |a Conditions particulières de réutilisation pour les bénéficiaires des licences nationales. chttps://www.licencesnationales.fr/springer-nature-ebooks-contrat-licence-ln-2017 | ||
| 520 | |a New manufacturing technologies have made possible the integration of entire systems on a single chip. This new design paradigm, termed system-on-chip (SOC), together with its associated manufacturing problems, represents a real challenge for designers. As well as giving rise to new design practices, SOC is also reshaping approaches to test and validation activities. These are beginning to migrate from the traditional register-transfer or gate levels of abstraction to the system level. Until now, test and validation have not been supported by system-level design tools so designers have lacked the necessary infrastructure to exploit all the benefits stemming from the adoption of the system level of abstraction such as higher functional performance and greater operating speed. Research efforts are already addressing this issue. System-level Test and Validation of Hardware/Software Systems provides a state-of-the-art overview of the current validation and test techniques by covering all aspects of the subject including: modeling of bugs and defects; stimulus generation for validation and test purposes (including timing errors; design for testability. For researchers working on system-level validation and testing, for tool vendors involved in developing hardware-software co-design tools and for graduate students working in embedded systems and SOC design and implementation, System-level Test and Validation of Hardware/Software Systems will be an invaluable source of reference. | ||
| 700 | 1 | |a Peng, Zebo. |4 pbd | |
| 700 | 1 | |a Violante, Massimo. |4 pbd | |
| 776 | 0 | |t System-level Test and Validation of Hardware/Software Systems |b Texte imprimé |z 9781849969536 | |
| 776 | 0 | |t System-level Test and Validation of Hardware/Software Systems |b Texte imprimé |z 9781848008076 | |
| 776 | 0 | |t System-level Test and Validation of Hardware/Software Systems |b Texte imprimé |z 9781852338992 | |
| 856 | 4 | |q PDF |u https://doi.org/10.1007/1-84628-145-8 |z Accès sur la plateforme de l'éditeur | |
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| 856 | 4 | |5 180339901:75149724X |u https://ezproxy.insa-cvl.fr/login?qurl=https://dx.doi.org/10.1007/1-84628-145-8 |z Accès INSA CVL | |
| 997 | |0 948040 |1 Livre numérique |a Ressource numérique |b INSA |b ENSA |c 0/Bibliothèque numérique/ |c 1/Bibliothèque numérique/Autre ressource numérique/ | ||