CMOS PLL synthesizers : analysis and design

CMOS PLL Synthesizers: Analysis and Design presents both fundamentals and state of the art PLL synthesizer design and analysis techniques. A complete overview of both system-level and circuit-level design and analysis are covered. A 16mW, 2.4GHz, sub-2V, S D fractional-N synthesizer prototype is imp...

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Auteurs principaux: Shu, Keliu, Sánchez-Sinencio, Edgar (Auteur)
Format: Livre numérique
Jezik:Anglais
Izdano: New York, NY : Springer US [20..].
Cham : Springer Nature
Izdaja:1st ed. 2005.
Serija:The Springer International Series in Engineering and Computer Science 783
Online dostop:Accès sur la plateforme de l'éditeur
Accès sur la plateforme Istex
Accès Université d'Orléans
Accès INSA CVL
Sporočilo: Archives Springer e-books (Licence nationale)
Archives Springer e-books (Licence nationale)
Autres localisations: Voir dans le Sudoc
Edition sous un autre format:• CMOS PLL synthesizers, analysis and design, Keliu Shu, Edgar Sánchez-Sinencio, New York, N.Y., Springer, 2005, 1 vol. (XVI, 215 p.), Springer international series in engineering and computer science, 0-387-23668-6
• CMOS PLL Synthesizers: Analysis and Design, Texte imprimé, 9781441936509
• Categorical algebra and its applications, proceedings of a conference, held in Louvain-La-Neuve, Belgium, July 26-August 1, 1987, F. Borceux (ed.), 1988, Berlin, Springer-Verlag, 1 volume (VIII-375 pages), Lecture notes in mathematics, 0-387-50362-5
• CMOS PLL synthesizers, analysis and design, Keliu Shu, Edgar Sánchez-Sinencio, New York, N.Y., Springer, 2005, 1 vol. (XVI, 215 p.), Springer international series in engineering and computer science, 0-387-23668-6
• CMOS PLL Synthesizers: Analysis and Design, Texte imprimé, 9781441936509
• Categorical algebra and its applications, proceedings of a conference, held in Louvain-La-Neuve, Belgium, July 26-August 1, 1987, F. Borceux (ed.), 1988, Berlin, Springer-Verlag, 1 volume (VIII-375 pages), Lecture notes in mathematics, 0-387-50362-5
• CMOS PLL synthesizers, analysis and design, Keliu Shu, Edgar Sánchez-Sinencio, New York, N.Y., Springer, 2005, 1 vol. (XVI, 215 p.), Springer international series in engineering and computer science, 0-387-23668-6
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505 1 |a Frequency Synthesizer for Wireless Applications PLL Frequency Synthesizer ?? Fractional-N PLL Synthesizer Enhanced Phase Switching Prescaler Loop Filter with Capacitance Multiplier Other Building Blocks of PLL Prototype Measurement Results Conclusions 
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520 |a CMOS PLL Synthesizers: Analysis and Design presents both fundamentals and state of the art PLL synthesizer design and analysis techniques. A complete overview of both system-level and circuit-level design and analysis are covered. A 16mW, 2.4GHz, sub-2V, S D fractional-N synthesizer prototype is implemented in 0.35mm CMOS. It features a high-speed and robust phase-switching prescaler, and a low-complexity and area-efficient loop capacitance mulitplier, which elegantly tackle speed and integration bottlenecks of PLL synthesizer. This book is useful as a PLL synthesizer manual for both academic researchers and industry design engineers 
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