Reconfigurable Computing: Architectures, Tools and Applications : 9th International Symposium, ARC 2013, Los Angeles, CA, USA, March 25-27, 2013. Proceedings
This book constitutes the thoroughly refereed conference proceedings of the 9th International Symposium on Reconfigurable Computing: Architectures, Tools and Applications, ARC 2013, held in Los Angeles, CA, USA, in March 2013. The 28 revised papers presented, consisting of 20 full papers and 11 post...
Salvato in:
| Altri autori: | , , |
|---|---|
| Natura: | Livre numérique |
| Lingua: | Anglais |
| Pubblicazione: |
Berlin, Heidelberg :
Springer Berlin Heidelberg
2013.
Cham : Springer Nature |
| Serie: | Theoretical Computer Science and General Issues
7806 |
| Accesso online: | Accès sur la plateforme de l'éditeur Accès sur la plateforme de l'éditeur (Springer) Accès sur la plateforme Istex Accès Université d'Orléans Accès INSA CVL |
| Nota: |
Archives Springer e-books (Licence nationale) Archives Springer e-books (Licence nationale) |
| Autres localisations: | Voir dans le Sudoc |
| Edition sous un autre format: | • Reconfigurable Computing: Architectures, Tools and Applications, Texte imprimé, 9783642368110 • Reconfigurable Computing: Architectures, Tools and Applications, Texte imprimé, 9783642368134 |
Sommario:
- Heterogeneous Reconfigurable System for Adaptive Particle Filters in Real-Time Applications
- Hardware Acceleration of Genetic Sequence Alignment
- An FPGA Acceleration for the Kd-tree Search in Photon Mapping
- SEU Resilience of DES, AES in SRAM-based FPGA
- An Architecture for IPv6 Lookup Using Parallel Index Generation Units
- Hardware Index to Set Partition Converter
- Teaching SoC Using Video Games to Improve Student Engagement
- Parameterized Design and Evaluation of Bandwidth Compressor for Floating-Point Data Streams in FPGA-based Custom Computing
- Hardware Acceleration of Matrix Multiplication Over Small Prime Finite Fields
- Flexible Design of a Modular Simultaneous Exponentiation Core for Embedded Platforms
- Architecture for Transparent Binary Acceleration of Loops with Memory Accesses
- Parametric Optimization of Reconfigurable Designs using Machine Learning
- Fast Template-based Heterogeneous MPSoC Synthesis on FPGA
- Hierarchical and Multiple Switching NoC with Floorplan based Adaptability
- Performance Analysis And Optimization of High Density Tree-Based 3D Multilevel FPGA.