Design, Analysis and Test of Logic Circuits Under Uncertainty
Integrated circuits (ICs) increasingly exhibit uncertain characteristics due to soft errors, inherently probabilistic devices, and manufacturing variability. As device technologies scale, these effects can be detrimental to the reliability of logic circuits. To improve future semiconductor designs,...
Sábháilte in:
| Príomhchruthaitheoirí: | , , |
|---|---|
| Formáid: | Livre numérique |
| Teanga: | Anglais |
| Foilsithe / Cruthaithe: |
Dordrecht :
Springer Netherlands
2013.
Cham : Springer Nature |
| Sraith: | Lecture Notes in Electrical Engineering
115 |
| Rochtain ar líne: | Accès sur la plateforme de l'éditeur Accès sur la plateforme Istex Accès Université d'Orléans Accès INSA CVL |
| Nóta: |
Archives Springer e-books (Licence nationale) Archives Springer e-books (Licence nationale) |
| Autres localisations: | Voir dans le Sudoc |
| Edition sous un autre format: | • Design, Analysis and Test of Logic Circuits Under Uncertainty, Texte imprimé, 9789048196432 • Design, Analysis and Test of Logic Circuits Under Uncertainty, Texte imprimé, 9789048196456 • Design, Analysis and Test of Logic Circuits Under Uncertainty, Texte imprimé, 9789400797987 |
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| 009 | PPN168335204 | ||
| 020 | |a 9789048196449 | ||
| 041 | 0 | |a eng | |
| 082 | |a 621.3815 | ||
| 100 | 1 | |a Krishnaswamy, Smita. | |
| 245 | 1 | 0 | |a Design, Analysis and Test of Logic Circuits Under Uncertainty |c by Smita Krishnaswamy, Igor L. Markov, John P. Hayes. |
| 260 | |a Dordrecht : |b Springer Netherlands. | ||
| 260 | |a Cham : |b Springer Nature, |c 2013. | ||
| 490 | 0 | |a Lecture Notes in Electrical Engineering |v 115 |x 1876-1119 | |
| 500 | |a Archives Springer e-books (Licence nationale) | ||
| 500 | |a Archives Springer e-books (Licence nationale) | ||
| 505 | 0 | |a Introduction -- Probabilistic Transfer Matrices -- Computing with Probabilistic Transfer Matrices -- Testing Logic Circuits for Probabilistic Faults -- Signtaure-based Reliability Analysis -- Design for Robustness -- Summary and Extensions. | |
| 506 | |a Accès en ligne pour les établissements français bénéficiaires des licences nationales | ||
| 506 | |a Accès soumis à abonnement pour tout autre établissement | ||
| 506 | |a Conditions particulières de réutilisation pour les bénéficiaires des licences nationales. chttps://www.licencesnationales.fr/springer-nature-ebooks-contrat-licence-ln-2017 | ||
| 520 | |a Integrated circuits (ICs) increasingly exhibit uncertain characteristics due to soft errors, inherently probabilistic devices, and manufacturing variability. As device technologies scale, these effects can be detrimental to the reliability of logic circuits. To improve future semiconductor designs, this book describes methods for analyzing, designing, and testing circuits subject to probabilistic effects. The authors first develop techniques to model inherently probabilistic methods in logic circuits and to test circuits for determining their reliability after they are manufactured. Then, they study error-masking mechanisms intrinsic to digital circuits and show how to leverage them to design more reliable circuits. The book describes techniques for: Modeling and reasoning about probabilistic behavior in logic circuits, including a matrix-based reliability-analysis framework; Accurate analysis of soft-error rate (SER) based on functional-simulation, sufficiently scalable for use in gate-level optimizations; Logic synthesis for greater resilience against soft errors, which improves reliability using moderate overhead in area and performance; Test-generation and test-compaction methods aimed at probabilistic faults in logic circuits that facilitate accurate and efficient post-manufacture measurement of soft-error susceptibility. | ||
| 700 | 1 | |a Markov, Igor L. |4 aut | |
| 700 | 1 | |a Hayes, John Patrick, |d 1944- |4 aut | |
| 776 | 0 | |t Design, Analysis and Test of Logic Circuits Under Uncertainty |b Texte imprimé |z 9789048196432 | |
| 776 | 0 | |t Design, Analysis and Test of Logic Circuits Under Uncertainty |b Texte imprimé |z 9789048196456 | |
| 776 | 0 | |t Design, Analysis and Test of Logic Circuits Under Uncertainty |b Texte imprimé |z 9789400797987 | |
| 856 | 4 | |q PDF |u https://doi.org/10.1007/978-90-481-9644-9 |z Accès sur la plateforme de l'éditeur | |
| 856 | 4 | |u https://revue-sommaire.istex.fr/ark:/67375/8Q1-DFNJKW0X-9 |z Accès sur la plateforme Istex | |
| 856 | 4 | |5 452349901:747899150 |u https://ezproxy.univ-orleans.fr/login?url=https://dx.doi.org/10.1007/978-90-481-9644-9 |z Accès Université d'Orléans | |
| 856 | 4 | |5 180339901:750912154 |u https://ezproxy.insa-cvl.fr/login?qurl=https://dx.doi.org/10.1007/978-90-481-9644-9 |z Accès INSA CVL | |
| 997 | |0 945990 |1 Livre numérique |a Ressource numérique |b INSA |b ENSA |c 0/Bibliothèque numérique/ |c 1/Bibliothèque numérique/Autre ressource numérique/ | ||