Computer aided verification : Fourth International Workshop, CAV '92, Montreal, Canada, June 29 July 1, 1992 : proceedings
This volume gives the proceedings of the Fourth Workshop on Computer-Aided Verification (CAV '92), held in Montreal, June 29 - July 1, 1992. The objective of this series of workshops is to bring together researchers and practitioners interested in the development and use of methods, tools and t...
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| Autres auteurs: | , |
| Format: | Livre numérique |
| Langue: | Anglais |
| Publié: |
Berlin [etc.] :
Springer
[20..].
Cham : Springer Nature |
| Collection: | Lecture notes in computer science
663 |
| Sujets: | |
| Accès en ligne: | Accès sur la plateforme de l'éditeur Accès sur la plateforme Istex Accès Université d'Orléans Accès INSA CVL |
| Note: |
Archives Springer e-books (Licence nationale) Archives Springer e-books (Licence nationale) |
| Autres localisations: | Voir dans le Sudoc |
| Edition sous un autre format: | • Computer aided verification, proceedings, Fourth International workshop, CAV '92, Montreal, Canada, June 29-July 1, 1992, Berlin, Springer-Verlag, 1993, 1 vol. (IX-422 p.), Lecture notes in computer science, 3-540-56496-9 • Computer Aided Verification, Texte imprimé, 9783662205792 |
Table des matières:
- Computer-hindered verification (humans can do it too)
- Modular abstractions for verifying real-time distributed systems
- Layering techniques for development of parallel systems
- Efficient local correctness checking
- Mechanical verification of concurrent systems with TLA
- Using a theorem prover for reasoning about concurrent algorithms
- Verifying a logic synthesis tool in Nuprl: A case study in software verification
- Higher-level specification and verification with BDDs
- Symbolic bisimulation minimisation
- Towards a verification technique for large synchronous circuits
- Verifying timed behavior automata with nonbinary delay constraints
- Timing verification by successive approximation
- A verification strategy for timing constrained systems
- Using unfoldings to avoid the state explosion problem in the verification of asynchronous circuits
- State space caching revisited
- Verification in process algebra of the distributed control of track vehicles A case study
- Design verification of a microprocessor using branching time regular temporal logic
- A case study in safety-critical design
- Automatic reduction in CTL compositional model checking
- Compositional model checking for linear-time temporal logic
- Property preserving simulations
- Verification with real-time COSPAN
- Model-checking for real-time systems specified in Lotos
- Decidability of bisimulation equivalences for parallel timer processes
- A proof assistant for symbolic model-checking
- Tableau recycling
- Crocos: An integrated environment for interactive verification of SDL specifications
- Verifying general safety and liveness properties with integer programming
- Generating diagnostic information for behavioral preorders
- A verification procedure via invariant for extended communicating finite-state machines
- Efficient ?-regular language containment
- Faster model checking for the modal Mu-Calculus.