VLSI algorithms and architectures : Aegean Workshop on Computing, Loutraki, Greece, July 8 11, 1986 : proceedings

Wedi'i Gadw mewn:
Manylion Llyfryddiaeth
Awdur Corfforaethol: Aegean workshop on computing :Loutraki
Awduron Eraill: Makedon, Fillia (Cyfarwyddwr cyhoeddi), Mehlhorn, Kurt, 1949- (Cyfarwyddwr cyhoeddi), Papatheodorou, Theodore S., 19..- (Cyfarwyddwr cyhoeddi)
Fformat: Livre numérique
Iaith:Anglais
Cyhoeddwyd: Berlin [etc.] : Springer [20..].
Cham : Springer Nature
Cyfres:Lecture notes in computer science 227
Pynciau:
Mynediad Ar-lein:Accès sur la plateforme de l'éditeur
Accès sur la plateforme Istex
Accès Université d'Orléans
Accès INSA CVL
Nodyn: Archives Springer e-books (Licence nationale)
Archives Springer e-books (Licence nationale)
Autres localisations: Voir dans le Sudoc
Edition sous un autre format:• VLSI algorithms and architectures, proceedings, of the Aegean Workshop on Computing, Loutraki, Greece, July 8-11, 1986 ; ed, by F. Makedon, K. Mehlhorn, T. Papatheodorou, P. Spirakis ; org, Berlin, Springer-Verlag, 1986, 1 Vol. (VIII-328 p.), Lecture notes in computer science, 3-540-16766-8
• VLSI Algorithms and Architectures, Texte imprimé, 9783662177525
Tabl Cynhwysion:
  • Digital filtering in VLSI
  • Two processor scheduling is in NC
  • Breaking symmetry in synchronous networks
  • Parallel ear decomposition search (EDS) and st-numbering in graphs
  • A unifying framework for systolic designs
  • Optimal tradeoffs for addition on systolic arrays
  • On the connection between hexagonal and unidirectional rectangular systolic arrays
  • Lower bounds for sorting on mesh-connected architectures
  • Diogenes, circa 1986 ????? ??? ??? ????o ????o?o
  • Nonsequential computation and laws of nature
  • Linear algorithms for two CMOS layout problems
  • Some new results on a restricted channel routing problem
  • Efficient modular design of TSC checkers for m-out-of-2m codes
  • Vlsi algorithms and pipelined architectures for solving structured linear system
  • A high-performance single-chip vlsi signal processor architecture
  • Exploiting hierarchy in VLSI design
  • A polynomial algorithm for recognizing images of polyhedra
  • Parallel tree techniques and code optimization
  • AT2-optimal galois field multiplier for VLSI
  • Linear and book embeddings of graphs
  • Efficient parallel evaluation of straight-line code and arithmetic circuits
  • A logarithmic boolean time algorithm for parallel polynomial division
  • A polynomial algorithm for recognizing small cutwidth in hypergraphs
  • A generalized topological sorting problem
  • Combinational static CMOS networks
  • Fast and efficient parallel linear programming and linear least squares computations
  • On the time required to sum n semigroup elements on a parallel machine with simultaneous writes
  • A comparative study of concurrency control methods in B-trees
  • Generalized river routing Algorithms and performance bounds.