Field-programmable logic and applications : 5th International Workshop, FPL '95 Oxford, United Kingdom, August 29 September 1, 1995 : proceedings
This volume constitutes the proceedings of the Fifth International Workshop on Field-Programmable Logic and Its Applications, FPL '95, held in Oxford, UK in August/September 1995. The volume presents 46 full revised papers carefully selected by the program committee from a large number and wide...
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| Kolejni autorzy: | , |
| Format: | Livre numérique |
| Język: | Anglais |
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Berlin [etc.] :
Springer
[20..].
Cham : Springer Nature |
| Seria: | Lecture notes in computer science
975 |
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| Dostęp online: | Accès sur la plateforme de l'éditeur Accès sur la plateforme Istex Accès Université d'Orléans Accès INSA CVL |
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| Edition sous un autre format: | • Field-programmable logic and applications, proceedings, 5th International workshop, FPL '95, Oxford, United Kingdom, August 29-September 1, 1995, [Berlin], Springer, 1995, 1 vol. (XII-450 p.), Lecture notes in computer science, 3-540-60294-1 • Field-Programmable Logic and Applications, Texte imprimé, 9783662174883 |
Spis treści:
- The design of a new FPGA architecture
- Migration of a dual granularity globally interconnected PLD architecture to a 0.5? TLM process
- Self-timed FPGA systems
- The XC6200 FastMap processor interface
- The Teramac configurable compute engine
- Telecommunication-oriented FPGA and dedicated CAD system
- A configurable logic processor for machine vision
- Extending DSP-boards with FPGA-based structures of interconnection
- High-speed region detection and labeling using an FPGA-based custom computing platform
- Using FPGAS as control support in MIMD executions
- Customised hardware based on the REDOC III algorithm for high performance data ciphering
- Using reconfigurable hardware to speed up product development and performance
- Creation of hardware objects in a reconfigurable computer
- Rapid hardware prototyping of Digital Signal Processing systems using Field Programmable Gate Arrays
- Delay minimal mapping of RTL structures onto LUT based FPGAs
- Some notes on power management on FPGA-based systems
- An automatic technique for realising user interaction processing in PLD based systems
- Proper use of hierarchy in HDL-based high density FGPA design
- Compiling regular arrays onto FPGAs
- Compiling Ruby into FPGAs
- The CSYN verilog compiler and other tools
- A VHDL design methodology for FPGAs
- VHDL-based rapid hardware prototyping using FPGA technology
- Integer programming for partitioning in software oriented codesign
- Test standard serves dual role as on-board programming solution
- Advanced method for industry related education with an FPGA design self-learning kit
- FPGA implementation of a rational adder
- FPLD-implementation of computations over finite fields GF(2m) with applications to error control coding
- Implementation of Fast Fourier Transforms andDiscrete Cosine Transforms in FPGAs
- Implementation of a 2-D fast Fourier transform on an FPGA-based custom computing machine
- An assessment of the suitability of FPGA-based systems for use in digital signal processing
- An FPGA prototype for a multiplierless FIR filter built using the logarithmic number system
- Bit-serial FIR filters with CSD coefficients for FPGAs
- A self-validating temperature sensor implemented in FPGAs
- Developing interface libraries for reconfigurable data acquisition boards
- Prototype generation of application specific embedded controllers for microsystems
- A hardware genetic algorithm for the traveling salesman problem on Splash 2
- Modular architecture for real-time astronomical image processing with FPGA
- A programmable I/O system for real-time AC drive control applications
- Reconfigurable logic for fault tolerance
- Supercomputing with reconfigurable architectures
- Automatic synthesis of parallel programs targeted to dynamically reconfigurable logic arrays
- Prototyping environment for dynamically reconfigurable logic
- Implementation approaches for reconfigurable logic applications
- Use of reconfigurability in variable-length code detection at video rates
- Classification and performance of reconfigurable architectures.