Hardware acceleration of EDA algorithms : custom ICs, FPGAs and GPUs
Hardware Acceleration of EDA Algorithms: Custom ICs, FPGAs and GPUs Kanupriya Gulati Sunil P. Khatri This book deals with the acceleration of EDA algorithms using hardware platforms such as Custom ICs, FPGAs and GPUs. Widely applied CAD algorithms are studied for potential acceleration on these plat...
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| Những tác giả chính: | , |
|---|---|
| Định dạng: | Livre numérique |
| Ngôn ngữ: | Anglais |
| Được phát hành: |
New York, NY :
Springer US
2010.
Cham : Springer Nature |
| Truy cập trực tuyến: | Accès sur la plateforme de l'éditeur Accès sur la plateforme Istex Accès Université d'Orléans Accès INSA CVL |
| Chú thích: |
Archives Springer e-books (Licence nationale) Archives Springer e-books (Licence nationale) |
| Autres localisations: | Voir dans le Sudoc |
| Edition sous un autre format: | • Hardware Acceleration of EDA Algorithms, Texte imprimé, 9781441909435 • Hardware Acceleration of EDA Algorithms, Texte imprimé, 9781441909459 • Hardware Acceleration of EDA Algorithms, Texte imprimé, 9781489983336 |
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| 008 | 110106s2010 xx ||| |||| 00| 0 eng d | ||
| 009 | PPN149075308 | ||
| 020 | |a 9781441909442 | ||
| 020 | |a 9781441909442 | ||
| 041 | 0 | |a eng | |
| 082 | |a 621.3815 | ||
| 100 | 1 | |a Gulati, Kanupriya. | |
| 245 | 1 | 0 | |a Hardware acceleration of EDA algorithms : |b custom ICs, FPGAs and GPUs |c by Kanupriya Gulati, Sunil P. Khatri. |
| 260 | |a New York, NY : |b Springer US. | ||
| 260 | |a Cham : |b Springer Nature, |c 2010. | ||
| 500 | |a Archives Springer e-books (Licence nationale) | ||
| 500 | |a Archives Springer e-books (Licence nationale) | ||
| 505 | 0 | |a Alternative Hardware Platforms -- Hardware Platforms -- GPU Architecture and the CUDA Programming Model -- Control Dominated Category -- Accelerating Boolean Satisfiability on a Custom IC -- Accelerating Boolean Satisfiability on an FPGA -- Accelerating Boolean Satisfiability on a Graphics Processing Unit -- Control Plus Data Parallel Applications -- Accelerating statistical static Timing Analysis Using Graphics Processors -- Accelerating Fault Simulation Using Graphics Processors -- Fault Table Generation Using Graphics Processors -- Accelerating Circuit Simulation Using Graphics Processors -- Automated Generation of GPU Code -- Automated Approach for Graphics Processor Based Software Acceleration -- Conclusions. | |
| 506 | |a Accès en ligne pour les établissements français bénéficiaires des licences nationales | ||
| 506 | |a Accès soumis à abonnement pour tout autre établissement | ||
| 506 | |a Conditions particulières de réutilisation pour les bénéficiaires des licences nationales. chttps://www.licencesnationales.fr/springer-nature-ebooks-contrat-licence-ln-2017 | ||
| 520 | |a Hardware Acceleration of EDA Algorithms: Custom ICs, FPGAs and GPUs Kanupriya Gulati Sunil P. Khatri This book deals with the acceleration of EDA algorithms using hardware platforms such as Custom ICs, FPGAs and GPUs. Widely applied CAD algorithms are studied for potential acceleration on these platforms. Coverage includes discussion of conditions under which it is preferable to use one platform over another, e.g., when an EDA problem has a high degree of data parallelism, the GPU is typically the preferred platform, whereas when the problem has more control, an FPGA may be preferred. Results are presented for the acceleration of several CAD algorithms (fault simulation, fault table generation, model card evaluation in SPICE, Monte Carlo based statistical static timing analysis, Boolean Satisfiability), demonstrating speedups up to 800X compared to single-core implementatinos of these algorithms. This book serves as a valuable guide on how best to leverage parallelism to accelerate CAD algorithms. It also presents a methodology to automatically extract SIMD parallelism from regular uniprocessor code which satisfies a set of constraints. With this approach, such uniprocessor code can automatically be converted to GPU code, allowing for significant acceleration. This approach is particularly useful since different GPUs have vastly different specifications, making the manual generation of GPU code an unscalable proposition. In particular, this book: Provides guidelines on whether to use Custom ICs, GPUs or FPGAs when accelerating a given EDA algorithm, validating these suggestions with a concrete example (Boolean Satisfiability) implemented on all these platforms; Demonstrates the acceleration of several popular EDA algorithms on GPUs, with speedups up to 800X; Helps the reader by presenting example algorithmswhich may be used by the reader to determine how best to accelerate their specific EDA algorithm; Discusses an automatic approach to generate GPU code, given regular uniprocessor code which satisfies a set of constraints; Serves as a valuable reference for anyone interested in exploring alternative hardware platforms for accelerating various EDA applications by harnessing the parallelism available in these platforms. | ||
| 700 | 1 | |a Khatri, Sunil P. |4 aut | |
| 776 | 0 | |t Hardware Acceleration of EDA Algorithms |b Texte imprimé |z 9781441909435 | |
| 776 | 0 | |t Hardware Acceleration of EDA Algorithms |b Texte imprimé |z 9781441909459 | |
| 776 | 0 | |t Hardware Acceleration of EDA Algorithms |b Texte imprimé |z 9781489983336 | |
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