Cellular Nanoscale Sensory Wave Computing

In this book the emerging and converging architecture of morphic cellular wave computers based on the concept of Cellular Neural/Nonlinear Network (CNN) is introduced in a practical way. The authors include descriptions of hardware architectures, software algorithms, as well as a possible new CNN ce...

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Tác giả chính: Baatar, Chagaan
Tác giả khác: Porod, Wolfgang (Biên tập viên), Roska, Tamás (Biên tập viên)
Định dạng: Livre numérique
Ngôn ngữ:Anglais
Được phát hành: Boston, MA : Springer US [20..].
Cham : Springer Nature
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Edition sous un autre format:• Cellular Nanoscale Sensory Wave Computing, Texte imprimé, 9781441910103
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505 1 |a A Brief History of CNN and ONR Cellular Wave Computing in Nanoscale via Million Processor Chips Nanoantenna Infrared Detectors Memristors: A New Nanoscale CNN Cell Circuit Models of Nanoscale Devices A CMOS Vision System On-Chip with Multi-Core, Cellular Sensory-Processing Front-End Cellular Multi-core Processor Carrier Chip for Nanoantenna Integration and Experiments Circuitry Underlying Visual Processing in the Retina Elastic Grid-Based Multi-Fovea Algorithm for Real-Time Object-Motion Detection in Airborne Surveillance Low-Power Processor Array Design Strategy for Solving Computationally Intensive 2D Topographic Problems 
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520 |a In this book the emerging and converging architecture of morphic cellular wave computers based on the concept of Cellular Neural/Nonlinear Network (CNN) is introduced in a practical way. The authors include descriptions of hardware architectures, software algorithms, as well as a possible new CNN cell based on memristor. The first single chip cellular wave computer- a vision system on a chip (VSoC) is also discussed. Cellular Nanoscale Sensory Wave Computing is a result of a Multidisciplinary University Research Initiative (MURI) project that has been funded by the Office of Naval Research and completed recently. The results manifest a new way of thinking about sensory computing, as well as it is one of the first successful attempts to bridge the gap between nanoscale (smaller than 100 nm) devices and CMOS integrated circuits with stored programmable algorithms and software on the system level 
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