Advances in Design Methods from Modeling Languages for Embedded Systems and SoC s : Selected Contributions on Specification, Design, and Verification from FDL 2009
More than ever, FDL is the place for researchers, developers, industry designers, academia, and EDA tool companies to present and to learn about the latest scientific achievements, practical applications and users experiences in the domain of specification and design languages. FDL covers the modeli...
Enregistré dans:
| Auteur principal: | |
|---|---|
| Autres auteurs: | |
| Format: | Livre numérique |
| Langue: | Anglais |
| Publié: |
Dordrecht :
Springer Netherlands : Springer e-books : Imprint: Springer : Springer e-books
[20..].
Cham : Springer Nature |
| Collection: | Lecture Notes in Electrical Engineering
63 |
| Accès en ligne: | Accès sur la plateforme de l'éditeur Accès sur la plateforme Istex Accès Université d'Orléans Accès INSA CVL |
| Note: |
Archives Springer e-books (Licence nationale) Archives Springer e-books (Licence nationale) |
| Autres localisations: | Voir dans le Sudoc |
| Edition sous un autre format: | • Advances in Design Methods from Modeling Languages for Embedded Systems and SoC s, Texte imprimé, 9789048193035 |
Table des matières:
- UML and MDE for Embedded Systems IP-XACT Components with Abstract Time Characterization MDE Support for HW/SW Codesign: A UML-based Design Flow C/C++-Based System Design Checkpoint and Restore for SystemC Models Efficient Approximately-Timed Performance Modeling for Architectural Exploration of MPSoCs Fast SystemC Performance Models for the Exploration of Embedded Memories Another Take on Functional System-Level Design and Modeling Design Automation Model for Application-Specific Processors on Reconfigurable Fabric A SystemC Superset for High-Level Synthesis Embedded Analog and Mixed-Signal System Design Design of Experiments for Effective Pre-silicon Verification of Automotive Electronics A VHDL-AMS Modeling Methodology for Top-Down/Bottom-Up Design of RF Systems Assertion Based Design, Verification & Debug High Level Synthesis Using Operation Properties A Re-Use Methodology for Formal SoC Protocol Compliance Verification ISIS: Runtime Verification of TLM Platforms SMT-based Stimuli Generation in the SystemC Verification Library