Network-on-Chip Architectures : A Holistic Design Exploration
The continuing reduction of feature sizes into the nanoscale regime has led to dramatic increases in transistor densities. Integration at these levels has highlighted the criticality of the on-chip interconnects. Network-on-Chip (NoC) architectures are viewed as a possible solution to burgeoning glo...
Guardat en:
| Autor principal: | |
|---|---|
| Format: | Livre numérique |
| Idioma: | Anglais |
| Publicat: |
Dordrecht :
Springer Netherlands
2010.
Cham : Springer Nature |
| Col·lecció: | Lecture Notes in Electrical Engineering
45 |
| Accés en línia: | Accès sur la plateforme de l'éditeur Accès sur la plateforme Istex Accès Université d'Orléans Accès INSA CVL |
| Nota: |
Archives Springer e-books (Licence nationale) Archives Springer e-books (Licence nationale) |
| Autres localisations: | Voir dans le Sudoc |
| Edition sous un autre format: | • Network-on-Chip Architectures, Texte imprimé, 9789048130320 • Network-on-Chip architectures, a holistic design exploration, Chrysostomos Nicopoulos, Vijaykrishnan Narayanan, Chita R. Das, Dordrecht, Springer, 2009, 1 vol. (XXI-223 p.), Lecture notes in electrical engineering, 978-90-481-3030-6 • Network-on-Chip Architectures, Texte imprimé, 9789400730496 |