Planar double-Gate transistor : from technology to circuit

This book on Double-Gates devices and circuit is unique and aims to reinforce the synergy between the research activities on CMOS sub-32nm devices and the design of elementary cells. The goal is to point out how we can take advantage of new transistor structures to come up with new basic cells and c...

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Altri autori: Amara, Amara (Direttore editoriale), Rozeau, Olivier, 19..-...., auteur en microélectronique (Direttore editoriale)
Natura: Livre numérique
Lingua:Anglais
Pubblicazione: Dordrecht : Springer Netherlands : Springer e-books [20..].
Cham : Springer Nature
Accesso online:Accès sur la plateforme de l'éditeur
Accès sur la plateforme Istex
Accès Université d'Orléans
Accès INSA CVL
Nota: Archives Springer e-books (Licence nationale)
Archives Springer e-books (Licence nationale)
Autres localisations: Voir dans le Sudoc
Edition sous un autre format:• Planar Double-Gate Transistor, From Technology to Circuit, edited by Amara Amara, Olivier Rozeau, [New-York], Springer, 2009, 1 vol. (viii-211 p.), 978-1-402-09327-2
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505 1 |a Multiple Gate Technologies Compact Modeling of Independent Double-Gate MOSFET: A Physical Approach Compact Modeling of Double Gate MOSFET for IC Design Low Frequency Noise in Double-Gate SOI CMOS Devices Analog Circuit Design Logic Circuit Design with DGMOS Devices SRAM Circuit Design 
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520 |a This book on Double-Gates devices and circuit is unique and aims to reinforce the synergy between the research activities on CMOS sub-32nm devices and the design of elementary cells. The goal is to point out how we can take advantage of new transistor structures to come up with new basic cells and concepts that exploit the electrical features of these new devices and the breakthrough they bring. Planar Double-Gate Transistor will mainly focus on SOI CMOS transistors, fully depleted with double independent planar Gates (Independent Planar Double Gates Transistors: IPDGT), a potential candidate for the sub-32 nm technological nodes as planned by the current ITRS Roadmap. The book topics are mainly focusing on: Detailed description of specific processes that allow the optimization of the CMOS IPDGT device CMOS IPDGT modeling, both compact and physical models are presented Device characterization Design of innovating cells (SRAM cells, basic digital & analog functions) with the objectives to improve the level of integration and the robustness to variability as well as the power consumption optimization, using the degree of freedom introduced by the independent gates 
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