Timing optimization through clock skew scheduling
Timing Optimization Through Clock Skew Scheduling focuses on optimizing the timing of large scale, high performance, digital synchronous systems. A particular emphasis is placed on algorithms for non-zero clock skew scheduling to improve the performance and reliability of VLSI circuits. This researc...
Enregistré dans:
| Auteurs principaux: | , , |
|---|---|
| Format: | Livre numérique |
| Sprog: | Anglais |
| Udgivet: |
New York, NY :
Springer US
2009.
Cham : Springer Nature |
| Online adgang: | Accès sur la plateforme de l'éditeur Accès sur la plateforme Istex Accès Université d'Orléans Accès INSA CVL |
| Kommentar: |
Archives Springer e-books (Licence nationale) Archives Springer e-books (Licence nationale) |
| Autres localisations: | Voir dans le Sudoc |
| Edition sous un autre format: | • Timing Optimization Through Clock Skew Scheduling, Texte imprimé, 9780387710556 • Timing Optimization Through Clock Skew Scheduling, Texte imprimé, 9780387565484 • Timing Optimization Through Clock Skew Scheduling, Texte imprimé, 9781441943774 |
Indholdsfortegnelse:
- VLSI Systems
- Signal Delay in VLSI Systems
- Timing Properties of Synchronous Systems
- Clock Skew Scheduling and Clock Tree Synthesis
- Clock Skew Scheduling of Level-Sensitive Circuits
- Clock Skew Scheduling for Improved Reliability
- Delay Insertion and Clock Skew Scheduling
- Practical Considerations
- Clock Skew Scheduling in Rotary Clocking Technology
- Experimental Results.