Generating hardware assertion checkers : for hardware verification, emulation, post-fabrication debugging and on-line monitoring
Assertion-based design is a powerful new paradigm that is facilitating quality improvement in electronic design. Assertions are statements used to describe properties of the design (I.e., design intent), that can be included to actively check correctness throughout the design cycle and even the life...
Gespeichert in:
| Hauptverfasser: | , |
|---|---|
| Format: | Livre numérique |
| Sprache: | Anglais |
| Veröffentlicht: |
Dordrecht :
Springer Netherlands
2008.
Cham : Springer Nature |
| Online Zugang: | Accès sur la plateforme de l'éditeur Accès sur la plateforme Istex Accès Université d'Orléans Accès INSA CVL |
| Anmerkung: |
Archives Springer e-books (Licence nationale) Archives Springer e-books (Licence nationale) |
| Autres localisations: | Voir dans le Sudoc |
| Edition sous un autre format: | • Generating Hardware Assertion Checkers, Texte imprimé, 9781402085857 • Generating Hardware Assertion Checkers, Texte imprimé, 9789048117611 • Generating Hardware Assertion Checkers, Texte imprimé, 9789048179220 |
Inhaltsangabe:
- Assertions and the Verification Landscape
- Basic Techniques Behind Assertion Checkers
- PSL and SVA Assertion Languages
- Automata for Assertion Checkers
- Construction of PSL Assertion Checkers
- Enhanced Features and Uses of PSL Checkers
- Evaluating and Verifying PSL Assertion Checkers
- Checkers for SystemVerilog Assertions
- Conclusions and Future Work.