Generating hardware assertion checkers : for hardware verification, emulation, post-fabrication debugging and on-line monitoring
Assertion-based design is a powerful new paradigm that is facilitating quality improvement in electronic design. Assertions are statements used to describe properties of the design (I.e., design intent), that can be included to actively check correctness throughout the design cycle and even the life...
Salvato in:
| Autori principali: | Boulé, Marc, 19..-, Zilic, Zeljko (Autore) |
|---|---|
| Natura: | Livre numérique |
| Lingua: | Anglais |
| Pubblicazione: |
Dordrecht :
Springer Netherlands
2008.
Cham : Springer Nature |
| Accesso online: | Accès sur la plateforme de l'éditeur Accès sur la plateforme Istex Accès Université d'Orléans Accès INSA CVL |
| Nota: |
Archives Springer e-books (Licence nationale) Archives Springer e-books (Licence nationale) |
| Autres localisations: | Voir dans le Sudoc |
| Edition sous un autre format: | • Generating Hardware Assertion Checkers, Texte imprimé, 9781402085857 • Generating Hardware Assertion Checkers, Texte imprimé, 9789048117611 • Generating Hardware Assertion Checkers, Texte imprimé, 9789048179220 |
Documenti analoghi
-
Verification by Error Modeling : Using Testing Techniques in Hardware Verification
(Livre numérique)
Radecka, Katarzyna, et al. -
Hardware verification with systemverilog : an object-oriented framework
(Livre numérique)
Mintz, Mike, et al.
Springer US, 2007 -
Formal hardware verification : methods and systems in comparison
(Livre numérique)
Kropf, Thomas, 1961- -
Chess Checkers Backgammon.
(Matériel)
Xinliye, 2022 -
Scalable Hardware Verification with Symbolic Simulation
(Livre numérique)
Bertacco, Valeria
Springer US, 2006

