Generating hardware assertion checkers : for hardware verification, emulation, post-fabrication debugging and on-line monitoring
Assertion-based design is a powerful new paradigm that is facilitating quality improvement in electronic design. Assertions are statements used to describe properties of the design (I.e., design intent), that can be included to actively check correctness throughout the design cycle and even the life...
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| Main Authors: | , |
|---|---|
| Format: | Livre numérique |
| Language: | Anglais |
| Published: |
Dordrecht :
Springer Netherlands
2008.
Cham : Springer Nature |
| Online Access: | Accès sur la plateforme de l'éditeur Accès sur la plateforme Istex Accès Université d'Orléans Accès INSA CVL |
| Note: |
Archives Springer e-books (Licence nationale) Archives Springer e-books (Licence nationale) |
| Autres localisations: | Voir dans le Sudoc |
| Edition sous un autre format: | • Generating Hardware Assertion Checkers, Texte imprimé, 9781402085857 • Generating Hardware Assertion Checkers, Texte imprimé, 9789048117611 • Generating Hardware Assertion Checkers, Texte imprimé, 9789048179220 |
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| 100 | 1 | |a Boulé, Marc, |d 19..- | |
| 245 | 1 | 0 | |a Generating hardware assertion checkers : |b for hardware verification, emulation, post-fabrication debugging and on-line monitoring |c by Marc Boulé, Zeljko Zilic. |
| 260 | |a Dordrecht : |b Springer Netherlands. | ||
| 260 | |a Cham : |b Springer Nature, |c 2008. | ||
| 500 | |a Archives Springer e-books (Licence nationale) | ||
| 500 | |a Archives Springer e-books (Licence nationale) | ||
| 505 | 0 | |a Assertions and the Verification Landscape -- Basic Techniques Behind Assertion Checkers -- PSL and SVA Assertion Languages -- Automata for Assertion Checkers -- Construction of PSL Assertion Checkers -- Enhanced Features and Uses of PSL Checkers -- Evaluating and Verifying PSL Assertion Checkers -- Checkers for SystemVerilog Assertions -- Conclusions and Future Work. | |
| 506 | |a Accès en ligne pour les établissements français bénéficiaires des licences nationales | ||
| 506 | |a Accès soumis à abonnement pour tout autre établissement | ||
| 506 | |a Conditions particulières de réutilisation pour les bénéficiaires des licences nationales. chttps://www.licencesnationales.fr/springer-nature-ebooks-contrat-licence-ln-2017 | ||
| 520 | |a Assertion-based design is a powerful new paradigm that is facilitating quality improvement in electronic design. Assertions are statements used to describe properties of the design (I.e., design intent), that can be included to actively check correctness throughout the design cycle and even the lifecycle of the product. With the appearance of two new languages, PSL and SVA, assertions have already started to improve verification quality and productivity. This is the first book that presents an under-the-hood view of generating assertion checkers, and as such provides a unique and consistent perspective on employing assertions in major areas, such as: specification, verification, debugging, on-line monitoring and design quality improvement. The PSL and SVA languages are treated in a unified way, thereby facilitating better learning and usage of the modern assertion languages, with a focus on obtaining the highest performance from assertion checkers. The obtained checkers are thoroughly benchmarked and verified, while formal proofs using automated reasoning techniques are explained. Included are examples of practical circuits (PCI, AMBA, Wishbone-PIC, CPU Pipeline) and their assertion checker synthesis. | ||
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| 776 | 0 | |t Generating Hardware Assertion Checkers |b Texte imprimé |z 9781402085857 | |
| 776 | 0 | |t Generating Hardware Assertion Checkers |b Texte imprimé |z 9789048117611 | |
| 776 | 0 | |t Generating Hardware Assertion Checkers |b Texte imprimé |z 9789048179220 | |
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