Closing the Power Gap Between ASIC & Custom : Tools and Techniques for Low Power Design
This book carefully details design tools and techniques for realizing low power and energy efficiency in a highly productive design methodology. Important topics include: - Microarchitectural techniques to reduce energy per operation - Power reduction with timing slack from pipelining - Analysis of...
Enregistré dans:
| Auteurs principaux: | , |
|---|---|
| Format: | Livre numérique |
| Langue: | Anglais |
| Publié: |
New York, NY :
Springer US
2007.
Cham : Springer Nature |
| Accès en ligne: | Accès sur la plateforme de l'éditeur Accès sur la plateforme Istex Accès Université d'Orléans Accès INSA CVL |
| Note: |
Archives Springer e-books (Licence nationale) Archives Springer e-books (Licence nationale) |
| Autres localisations: | Voir dans le Sudoc |
| Edition sous un autre format: | • Closing the Power Gap Between ASIC & Custom, Texte imprimé, 9780387506937 • Closing the Power Gap Between ASIC & Custom, Texte imprimé, 9781441938336 • Closing the Power Gap between ASIC & Custom, Texte imprimé, 9780387257631 |
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| 100 | 1 | |a Chinnery, David. | |
| 245 | 1 | 0 | |a Closing the Power Gap Between ASIC & Custom : |b Tools and Techniques for Low Power Design |c by David Chinnery, Kurt Keutzer. |
| 260 | |a New York, NY : |b Springer US. | ||
| 260 | |a Cham : |b Springer Nature, |c 2007. | ||
| 500 | |a Archives Springer e-books (Licence nationale) | ||
| 500 | |a Archives Springer e-books (Licence nationale) | ||
| 505 | 0 | |a Overview of the Factors Affecting the Power Consumption -- Pipelining to Reduce the Power -- Voltage Scaling -- Methodology to Optimize Energy of Computation for SOCs -- Linear Programming for Gate Sizing -- Linear Programming for Multi-Vth and Multi-Vdd Assignment -- Power Optimization using Multiple Supply Voltages -- Placement for Power Optimization -- Power Gating Design Automation -- Verification For Multiple Supply Voltage Designs -- Winning the Power Struggle in an Uncertain Era -- Pushing ASIC Performance in a Power Envelope -- Low Power ARM 1136JF-S Design. | |
| 506 | |a Accès en ligne pour les établissements français bénéficiaires des licences nationales | ||
| 506 | |a Accès soumis à abonnement pour tout autre établissement | ||
| 506 | |a Conditions particulières de réutilisation pour les bénéficiaires des licences nationales. chttps://www.licencesnationales.fr/springer-nature-ebooks-contrat-licence-ln-2017 | ||
| 520 | |a This book carefully details design tools and techniques for realizing low power and energy efficiency in a highly productive design methodology. Important topics include: - Microarchitectural techniques to reduce energy per operation - Power reduction with timing slack from pipelining - Analysis of the benefits of using multiple supply and threshold voltages - Placement techniques for multiple supply voltages - Verification for multiple voltage domains - Improved algorithms for gate sizing, and assignment of supply and threshold voltages - Power gating design automation to reduce leakage - Relationships among statistical timing, power analysis, and parametric yield optimization Design examples illustrate that these techniques can improve energy efficiency by two to three times. | ||
| 700 | 1 | |a Keutzer, Kurt William, |d 1955- |4 aut | |
| 776 | 0 | |t Closing the Power Gap Between ASIC & Custom |b Texte imprimé |z 9780387506937 | |
| 776 | 0 | |t Closing the Power Gap Between ASIC & Custom |b Texte imprimé |z 9781441938336 | |
| 776 | 0 | |t Closing the Power Gap between ASIC & Custom |b Texte imprimé |z 9780387257631 | |
| 856 | 4 | |q PDF |u https://doi.org/10.1007/978-0-387-68953-1 |z Accès sur la plateforme de l'éditeur | |
| 856 | 4 | |u https://revue-sommaire.istex.fr/ark:/67375/8Q1-J7G3X5QK-Q |z Accès sur la plateforme Istex | |
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