Full-Chip Nanometer Routing Techniques
As Moore's Law continues unencumbered into the nanometer era, chips are reaching 1000 M gates in size, process geometries have shrunk to 90 nm and below, and engineers have to face compounded design complexity with every new design. These nanometer-scale designs require a new generation of phys...
Guardado en:
| Autores principales: | , , |
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| Formato: | Livre numérique |
| Lenguaje: | Anglais |
| Publicado: |
Dordrecht :
Springer Netherlands
2007.
Cham : Springer Nature |
| Colección: | Analog Circuits and Signal Processing
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| Acceso en línea: | Accès sur la plateforme de l'éditeur Accès sur la plateforme Istex Accès Université d'Orléans Accès INSA CVL |
| Nota: |
Archives Springer e-books (Licence nationale) Archives Springer e-books (Licence nationale) |
| Autres localisations: | Voir dans le Sudoc |
| Edition sous un autre format: | • Full-Chip Nanometer Routing Techniques, Texte imprimé, 9789048175628 • Full-Chip Nanometer Routing Techniques, Texte imprimé, 9789048113958 • Full-Chip Nanometer Routing Techniques, Texte imprimé, 9781402061943 |
Tabla de Contenidos:
- Routing Challenges for Nanometer Technology
- Multilevel Full-Chip Routing Considering Crosstalk And Performance
- Multilevel Full-Chip Routing Considering Antenna Effect Avoidance
- Multilevel Full-Chip Routing For The X-Based Architecture
- Concluding Remarks And Future Work.