Full-Chip Nanometer Routing Techniques
As Moore's Law continues unencumbered into the nanometer era, chips are reaching 1000 M gates in size, process geometries have shrunk to 90 nm and below, and engineers have to face compounded design complexity with every new design. These nanometer-scale designs require a new generation of phys...
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| Auteurs principaux: | , , |
|---|---|
| Formato: | Livre numérique |
| Idioma: | Anglais |
| Publicado em: |
Dordrecht :
Springer Netherlands
2007.
Cham : Springer Nature |
| Colecção: | Analog Circuits and Signal Processing
|
| Acesso em linha: | Accès sur la plateforme de l'éditeur Accès sur la plateforme Istex Accès Université d'Orléans Accès INSA CVL |
| Nota: |
Archives Springer e-books (Licence nationale) Archives Springer e-books (Licence nationale) |
| Autres localisations: | Voir dans le Sudoc |
| Edition sous un autre format: | • Full-Chip Nanometer Routing Techniques, Texte imprimé, 9789048175628 • Full-Chip Nanometer Routing Techniques, Texte imprimé, 9789048113958 • Full-Chip Nanometer Routing Techniques, Texte imprimé, 9781402061943 |
| LEADER | 04019nam a22003737a 4500 | ||
|---|---|---|---|
| 001 | 938965 | ||
| 008 | 080410s2007 xx ||| |||| 00| 0 eng d | ||
| 009 | PPN123150558 | ||
| 020 | |a 9781402061950 | ||
| 020 | |a 9781402061950 | ||
| 041 | 0 | |a eng | |
| 082 | |a 621.3815 | ||
| 100 | 1 | |a Ho, Tsung-Yi, |d 19..- | |
| 245 | 1 | 0 | |a Full-Chip Nanometer Routing Techniques |c by Tsung-Yi Ho, Yao-Wen Chang, Sao-Jie Chen,... |
| 260 | |a Dordrecht : |b Springer Netherlands. | ||
| 260 | |a Cham : |b Springer Nature, |c 2007. | ||
| 490 | 0 | |a Analog Circuits and Signal Processing |x 2197-1854 | |
| 500 | |a Archives Springer e-books (Licence nationale) | ||
| 500 | |a Archives Springer e-books (Licence nationale) | ||
| 505 | 0 | |a Routing Challenges for Nanometer Technology -- Multilevel Full-Chip Routing Considering Crosstalk And Performance -- Multilevel Full-Chip Routing Considering Antenna Effect Avoidance -- Multilevel Full-Chip Routing For The X-Based Architecture -- Concluding Remarks And Future Work. | |
| 506 | |a Accès en ligne pour les établissements français bénéficiaires des licences nationales | ||
| 506 | |a Accès soumis à abonnement pour tout autre établissement | ||
| 506 | |a Conditions particulières de réutilisation pour les bénéficiaires des licences nationales. chttps://www.licencesnationales.fr/springer-nature-ebooks-contrat-licence-ln-2017 | ||
| 520 | |a As Moore's Law continues unencumbered into the nanometer era, chips are reaching 1000 M gates in size, process geometries have shrunk to 90 nm and below, and engineers have to face compounded design complexity with every new design. These nanometer-scale designs require a new generation of physics-aware and manufacturing-aware routing. At 90 nm and below, there are so many signal-integrity issues that design teams cannot manually correct them all. At 90 nm, wires account for nearly 75% of the total delay in a circuit. Even more insidious, however, is that among nearly 40% of these nets, more than 50% of their total net capacitance are attributed to the cross-coupling capacitance between neighboring signals. At this point a new design and optimization paradigm based on real wires is required. Nanometer routers must prevent and correct these effects on-the-fly in order to reach timing closure. From a manufacturability standpoint, nanometer routers must explicitly deal with the ever increasing design complexity, and be capable of adapting to the constraint requirements of timing, signal integrity, process antenna effect, and new interconnect architecture such as X-architecture. In the nanometer era, we must look into new-generation routing technologies that combine high performance and capacity with the integration of congestion, timing, SI prevention, and DFM algorithms as the best means of getting to design closure quickly. In this book, we present a novel multilevel full-chip router, namely mSIGMA for SIGnal-integrity and MAnufacturability optimization. And these routing technologies will ensure faster time-to-market and time-to-profitability. | ||
| 700 | 1 | |a Chang, Yao-Wen, |d 1966- |4 aut | |
| 700 | 1 | |a Chen, Sao-Jie. |4 aut | |
| 776 | 0 | |t Full-Chip Nanometer Routing Techniques |b Texte imprimé |z 9789048175628 | |
| 776 | 0 | |t Full-Chip Nanometer Routing Techniques |b Texte imprimé |z 9789048113958 | |
| 776 | 0 | |t Full-Chip Nanometer Routing Techniques |b Texte imprimé |z 9781402061943 | |
| 856 | 4 | |q PDF |u https://doi.org/10.1007/978-1-4020-6195-0 |z Accès sur la plateforme de l'éditeur | |
| 856 | 4 | |u https://revue-sommaire.istex.fr/ark:/67375/8Q1-KQW0D5KL-P |z Accès sur la plateforme Istex | |
| 856 | 4 | |5 452349901:747887551 |u https://ezproxy.univ-orleans.fr/login?url=https://dx.doi.org/10.1007/978-1-4020-6195-0 |z Accès Université d'Orléans | |
| 856 | 4 | |5 180339901:750900571 |u https://ezproxy.insa-cvl.fr/login?qurl=https://dx.doi.org/10.1007/978-1-4020-6195-0 |z Accès INSA CVL | |
| 997 | |0 938965 |1 Livre numérique |a Ressource numérique |b INSA |b ENSA |c 0/Bibliothèque numérique/ |c 1/Bibliothèque numérique/Autre ressource numérique/ | ||