Modern circuit placement : best practices and results
Modern Circuit Placement: Best Practices and Results describes advanced techniques in VLSI circuit placement which is one of the most important steps of the VLSI physical design flow. Physical design addresses the back-end layout stage of the chip design process. As technology scales down, the signi...
Zapisane w:
| Główni autorzy: | , |
|---|---|
| Format: | Livre numérique |
| Język: | Anglais |
| Wydane: |
New York, NY :
Springer US
[20..].
Cham : Springer Nature |
| Wydanie: | 1st ed. 2007. |
| Seria: | Series on Integrated Circuits and Systems
|
| Dostęp online: | Accès sur la plateforme de l'éditeur Accès sur la plateforme Istex Accès Université d'Orléans Accès INSA CVL |
| Komentarz: |
Archives Springer e-books (Licence nationale) Archives Springer e-books (Licence nationale) |
| Autres localisations: | Voir dans le Sudoc |
| Edition sous un autre format: | • Modern Circuit Placement, Texte imprimé, 9780387368375 • Modern Circuit Placement, Texte imprimé, 9780387515366 • Modern Circuit Placement, Texte imprimé, 9781441942319 |
Spis treści:
- Benchmarks ISPD 2005/2006 Placement Benchmarks Locality and Utilization in Placement Suboptimality Flat Placement Techniques DPlace: Anchor Cell-Based Quadratic Placement with Linear Objective Kraftwerk: A Fast and Robust Quadratic Placer Using an Exact Linear Net Model Top-Down Partitioning-Based Techniques Capo: Congestion-Driven Placement for Standard-cell and RTL Netlists with Incremental Capability Congestion Minimization in Modern Placement Circuits Multilevel Placement Techniques APlace: A High Quality, Large-Scale Analytical Placer FastPlace: An Efficient Multilevel Force-Directed Placement Algorithm mFAR: Multilevel Fixed-Points Addition-Based VLSI Placement mPL6: Enhanced Multilevel Mixed-Size Placement with Congestion Control NTUplace3: An Analytical Placer for Large-Scale Mixed-Size Designs Conclusion and Challenges.