Fast, efficient and predictable memory accesses : optimization algorithms for memory architecture aware compilation
Fast, Efficient and Predictable Memory Accesses presents techniques for designing fast, energy-efficient and timing predictable memory systems. By using a careful combination of compiler optimizations and architectural improvements, we can achieve more than what would be feasible at one of the level...
Guardat en:
| Autors principals: | , |
|---|---|
| Format: | Livre numérique |
| Idioma: | Anglais |
| Publicat: |
Dordrecht :
Springer Netherlands
2006.
Cham : Springer Nature |
| Accés en línia: | Accès sur la plateforme de l'éditeur Accès sur la plateforme Istex Accès Université d'Orléans Accès INSA CVL |
| Nota: |
Archives Springer e-books (Licence nationale) Archives Springer e-books (Licence nationale) |
| Autres localisations: | Voir dans le Sudoc |
| Edition sous un autre format: | • Fast, Efficient and Predictable Memory Accesses, Texte imprimé, 9781402048210 • Fast, Efficient and Predictable Memory Accesses, Texte imprimé, 9789048108787 • Fast, Efficient and Predictable Memory Accesses, Texte imprimé, 9789048172009 |
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| 008 | 080410s2006 xx ||| |||| 00| 0 eng d | ||
| 009 | PPN123115868 | ||
| 020 | |a 9781402048227 | ||
| 020 | |a 9781402048227 | ||
| 041 | 0 | |a eng | |
| 082 | |a 621.3815 | ||
| 100 | 1 | |a Wehmeyer, Lars. | |
| 245 | 1 | 0 | |a Fast, efficient and predictable memory accesses : |b optimization algorithms for memory architecture aware compilation |c by Lars Wehmeyer, Peter Marwedel. |
| 260 | |a Dordrecht : |b Springer Netherlands. | ||
| 260 | |a Cham : |b Springer Nature, |c 2006. | ||
| 500 | |a Archives Springer e-books (Licence nationale) | ||
| 500 | |a Archives Springer e-books (Licence nationale) | ||
| 505 | 0 | |a Abstract -- Models and Tools -- Scratchpad Memory Optimizations -- Main Memory Optimizations -- Register File Optimization -- Summary -- Future Work. | |
| 506 | |a Accès en ligne pour les établissements français bénéficiaires des licences nationales | ||
| 506 | |a Accès soumis à abonnement pour tout autre établissement | ||
| 506 | |a Conditions particulières de réutilisation pour les bénéficiaires des licences nationales. chttps://www.licencesnationales.fr/springer-nature-ebooks-contrat-licence-ln-2017 | ||
| 520 | |a Fast, Efficient and Predictable Memory Accesses presents techniques for designing fast, energy-efficient and timing predictable memory systems. By using a careful combination of compiler optimizations and architectural improvements, we can achieve more than what would be feasible at one of the levels in isolation. The described optimization algorithms achieve the goals of high performance and low energy consumption. In addition to these benefits, the use of scratchpad memories significantly improves the timing predictability of the entire system, leading to tighter worst case execution time bounds (WCET). The WCET is a relevant design parameter for all timing critical systems. In addition, the book covers algorithms to exploit the power down modes of main memories in SDRAM technology, as well as the execute-in-place feature of Flash memories. The final chapter considers the impact of the register file, which is also part of the memory hierarchy. | ||
| 700 | 1 | |a Marwedel, Peter. |4 aut | |
| 776 | 0 | |t Fast, Efficient and Predictable Memory Accesses |b Texte imprimé |z 9781402048210 | |
| 776 | 0 | |t Fast, Efficient and Predictable Memory Accesses |b Texte imprimé |z 9789048108787 | |
| 776 | 0 | |t Fast, Efficient and Predictable Memory Accesses |b Texte imprimé |z 9789048172009 | |
| 856 | 4 | |q PDF |u https://doi.org/10.1007/1-4020-4822-X |z Accès sur la plateforme de l'éditeur | |
| 856 | 4 | |u https://revue-sommaire.istex.fr/ark:/67375/8Q1-DZRMP73F-T |z Accès sur la plateforme Istex | |
| 856 | 4 | |5 452349901:747902712 |u https://ezproxy.univ-orleans.fr/login?url=https://dx.doi.org/10.1007/1-4020-4822-X |z Accès Université d'Orléans | |
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