Writing Testbenches using System Verilog :: SCD d'Orléans

Writing Testbenches using System Verilog

Writing Testbenches using System Verilog

Verification is too often approached in an ad hoc fashion. Visually inspecting simulation results is no longer feasible and the directed test-case methodology is reaching its limit. Moore's Law demands a productivity revolution in functional verification methodology. Writing Testbenches Using S...

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Autore principale:	Bergeron, Janick
Natura:	Livre numérique
Lingua:	Anglais
Pubblicazione:	New York, NY : Springer US : Imprint: Springer [20..]. Cham : Springer Nature
Accesso online:	Accès sur la plateforme de l'éditeur Accès sur la plateforme Istex Accès Université d'Orléans Accès INSA CVL
Nota:	Archives Springer e-books (Licence nationale) Archives Springer e-books (Licence nationale)
Autres localisations:	Voir dans le Sudoc
Edition sous un autre format:	• Writing Testbenches using SystemVerilog, Texte imprimé, 9780387509969 • Writing Testbenches using SystemVerilog, Texte imprimé, 9781441939784 • Writing testbenches using System Verilog, by Janick Bergeron,..., New York, Springer, 2006, 1 vol. (xxvi-412 p.), 0-387-29221-7

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