Scalable Hardware Verification with Symbolic Simulation
Scalable Hardware Verification with Symbolic Simulation presents recent advancements in symbolic simulation-based solutions which radically improve scalability. It overviews current verification techniques, both based on logic simulation and formal verification methods, and unveils the inner working...
محفوظ في:
| المؤلف الرئيسي: | |
|---|---|
| التنسيق: | Livre numérique |
| اللغة: | Anglais |
| منشور في: |
New York, NY :
Springer US
2006.
Cham : Springer Nature |
| الوصول للمادة أونلاين: | Accès sur la plateforme de l'éditeur Accès sur la plateforme Istex Accès Université d'Orléans Accès INSA CVL |
| ملاحظة: |
Archives Springer e-books (Licence nationale) Archives Springer e-books (Licence nationale) |
| Autres localisations: | Voir dans le Sudoc |
| Edition sous un autre format: | • Scalable Hardware Verification with Symbolic Simulation, Texte imprimé, 9780387244112 • Scalable Hardware Verification with Symbolic Simulation, Texte imprimé, 9780387505053 • Scalable Hardware Verification with Symbolic Simulation, Texte imprimé, 9781441937391 |
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| 100 | 1 | |a Bertacco, Valeria. | |
| 245 | 1 | 0 | |a Scalable Hardware Verification with Symbolic Simulation |c by Valeria Bertacco. |
| 260 | |a New York, NY : |b Springer US. | ||
| 260 | |a Cham : |b Springer Nature, |c 2006. | ||
| 500 | |a Archives Springer e-books (Licence nationale) | ||
| 500 | |a Archives Springer e-books (Licence nationale) | ||
| 505 | 0 | |a Design and Verification of Digital Systems -- Symbolic Simulation -- Compacting Intermediate States -- Approximate Simulation -- Exact Parametrizations -- Conclusion. | |
| 506 | |a Accès en ligne pour les établissements français bénéficiaires des licences nationales | ||
| 506 | |a Accès soumis à abonnement pour tout autre établissement | ||
| 506 | |a Conditions particulières de réutilisation pour les bénéficiaires des licences nationales. chttps://www.licencesnationales.fr/springer-nature-ebooks-contrat-licence-ln-2017 | ||
| 520 | |a Scalable Hardware Verification with Symbolic Simulation presents recent advancements in symbolic simulation-based solutions which radically improve scalability. It overviews current verification techniques, both based on logic simulation and formal verification methods, and unveils the inner workings of symbolic simulation. The core of this book focuses on new techniques that narrow the performance gap between the complexity of digital systems and the limited ability to verify them. In particular, it covers a range of solutions that exploit approximation and parametrization methods, including quasi-symbolic simulation, cycle-based symbolic simulation, and parameterizations based on disjoint-support decompositions. In structuring this book, the author s hope was to provide interesting reading for a broad range of design automation readers. The first two chapters provide an overview of digital systems design and, in particular, verification. Chapter 3 reviews mainstream symbolic techniques in formal verification, dedicating most of its focus to symbolic simulation. The fourth chapter covers the necessary principles of parametric forms and disjoint-support decompositions. Chapters 5 and 6 focus on recent symbolic simulation techniques, and the final chapter addresses key topics needing further research. Scalable Hardware Verification with Symbolic Simulation is for verification engineers and researchers in the design automation field. | ||
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| 776 | 0 | |t Scalable Hardware Verification with Symbolic Simulation |b Texte imprimé |z 9780387505053 | |
| 776 | 0 | |t Scalable Hardware Verification with Symbolic Simulation |b Texte imprimé |z 9781441937391 | |
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| 856 | 4 | |u https://revue-sommaire.istex.fr/ark:/67375/8Q1-MPS0J2HK-N |z Accès sur la plateforme Istex | |
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