Computer architecture : a quantitative approach

Computer Architecture: A Quantitative Approach, Sixth Edition has been considered essential reading by instructors, students and practitioners of computer design for over 20 years. The sixth edition of this classic textbook from Hennessy and Patterson, winners of the 2017 ACM A.M. Turing Award recog...

תיאור מלא

שמור ב:
מידע ביבליוגרפי
Auteurs principaux: Hennessy, John L., 1952-, Patterson, David A., 1947- (Auteur)
פורמט: Livre numérique
שפה:Anglais
יצא לאור: Cambridge (Mass.) : Morgan Kaufmann Publishers, an imprint of Elsevier : Elsevier 2017.
Paris : Cyberlibris
נושאים:
גישה מקוונת:Accès Université d'Orléans et IFPM
הערה: Couverture. https://static2.cyberlibris.com/books_upload/300pix/9780128119068.jpg
Cyberlibris (ScholarVox) corpus Informatique
Autres localisations: Voir dans le Sudoc
Edition sous un autre format:• Computer architecture, a quantitative approach, John L. Hennessy,... David A. Patterson,..., Sixth edition, 2019, Cambridge (Mass.), Morgan Kaufmann Publishers, an imprint of Elsevier, Elsevier, 1 vol. (XXIII- 617-[325] p.), 978-0-12-811905-1
תוכן הענינים:
  • Chapter 1. Fundamentals of quantitative design and analysis
  • Chapter 2. Memory hierarchy design
  • Chapter 3. Instruction-level parallelism and its exploitation
  • Chapter 4. Data-level parallelism in vector, SIMD, and GPU architectures
  • Chapter 5. Thread-level parallelism
  • Chapter 6. Warehouse-scale computers to exploit request-level and data-level parallelism
  • Chapter 7. Domain-specific architectures
  • Appendix A. Instruction set principles
  • Appendix B. Review of memory hierarchy
  • Appendix C. Pipelining : basic and intermediate concepts
  • Appendix D. Storage systems
  • Appendix E. Embedded systems
  • Appendix F. Interconnection networks
  • Appendix G. Vector processors in more depth
  • Appendix H. Hardware and software for VLIM and EPIC
  • Appendix I. Large-scale multiprocessors and scientific applications
  • Appendix J. Computer arithmétic
  • Appendix K. Survey of instruction set architectures
  • Appendix L. Advanced concepts on address translation
  • Appendix M. Historical perspectives and references